Re: [PATCH v2 03/11] clk: qcom: ipq8074: fix missing GPLL0 divider width
From: Stephen Boyd
Date: Thu Dec 21 2017 - 19:26:20 EST
On 12/13, Abhishek Sahu wrote:
> GPLL0 uses 4 bits post divider which should be specified
> in clock driver structure.
>
> Signed-off-by: Abhishek Sahu <absahu@xxxxxxxxxxxxxx>
> ---
Applied to clk-next
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