[PATCH v3 28/34] clk: ti: fapll: change round_rate() return logic

[Bryan O'Donoghue]

This patch updates the round_rate() logic here to return zero instead of a
negative number on error.

In conjunction with higher-level changes associated with acting on the
return value of clk_ops->round_rate() it is then possible to have
clk_ops->round_rate() return values from 1 Hz to ULONG_MAX Hz instead of
the current limitation of 1 Hz to LONG_MAX Hz.

Signed-off-by: Bryan O'Donoghue <pure.logic@xxxxxxxxxxxxxxxxx>
Cc: Tero Kristo <t-kristo@xxxxxx>
Cc: Michael Turquette <mturquette@xxxxxxxxxxxx>
Cc: Stephen Boyd <sboyd@xxxxxxxxxxxxxx>
Cc: Tony Lindgren <tony@xxxxxxxxxxx>
Cc: linux-omap@xxxxxxxxxxxxxxx
Cc: linux-clk@xxxxxxxxxxxxxxx
Cc: linux-kernel@xxxxxxxxxxxxxxx
---
 drivers/clk/ti/fapll.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/drivers/clk/ti/fapll.c b/drivers/clk/ti/fapll.c
index 2e74437..f435a8c 100644
--- a/drivers/clk/ti/fapll.c
+++ b/drivers/clk/ti/fapll.c
@@ -227,12 +227,12 @@ static unsigned long ti_fapll_round_rate(struct clk_hw *hw, unsigned long rate,
 	int error;
 
 	if (!rate)
-		return -EINVAL;
+		return 0;
 
 	error = ti_fapll_set_div_mult(rate, *parent_rate,
 				      &pre_div_p, &mult_n);
 	if (error)
-		return error;
+		return 0;
 
 	rate = *parent_rate / pre_div_p;
 	rate *= mult_n;
@@ -414,7 +414,7 @@ static unsigned long ti_fapll_synth_round_rate(struct clk_hw *hw,
 	unsigned long r;
 
 	if (ti_fapll_clock_is_bypass(fd) || !synth->div || !rate)
-		return -EINVAL;
+		return 0;
 
 	/* Only post divider m available with no fractional divider? */
 	if (!synth->freq) {
-- 
2.7.4