[tip:x86/pti] x86/pti: Switch to kernel CR3 at early in entry_SYSCALL_compat()

[tip-bot for Thomas Gleixner]

Commit-ID:  d7732ba55c4b6a2da339bb12589c515830cfac2c
Gitweb:     https://git.kernel.org/tip/d7732ba55c4b6a2da339bb12589c515830cfac2c
Author:     Thomas Gleixner <tglx@xxxxxxxxxxxxx>
AuthorDate: Wed, 3 Jan 2018 19:52:04 +0100
Committer:  Thomas Gleixner <tglx@xxxxxxxxxxxxx>
CommitDate: Wed, 3 Jan 2018 23:19:32 +0100

x86/pti: Switch to kernel CR3 at early in entry_SYSCALL_compat()

The preparation for PTI which added CR3 switching to the entry code
misplaced the CR3 switch in entry_SYSCALL_compat().

With PTI enabled the entry code tries to access a per cpu variable after
switching to kernel GS. This fails because that variable is not mapped to
user space. This results in a double fault and in the worst case a kernel
crash.

Move the switch ahead of the access and clobber RSP which has been saved
already.

Fixes: 8a09317b895f ("x86/mm/pti: Prepare the x86/entry assembly code for entry/exit CR3 switching")
Reported-by: Lars Wendler <wendler.lars@xxxxxx>
Reported-by: Laura Abbott <labbott@xxxxxxxxxx>
Signed-off-by: Thomas Gleixner <tglx@xxxxxxxxxxxxx>
Cc: Borislav Betkov <bp@xxxxxxxxx>
Cc: Andy Lutomirski <luto@xxxxxxxxxx>, 
Cc: Dave Hansen <dave.hansen@xxxxxxxxxxxxxxx>, 
Cc: Peter Zijlstra <peterz@xxxxxxxxxxxxx>, 
Cc: Greg KH <gregkh@xxxxxxxxxxxxxxxxxxx>, , 
Cc: Boris Ostrovsky <boris.ostrovsky@xxxxxxxxxx>, 
Cc: Juergen Gross <jgross@xxxxxxxx>
Cc: stable@xxxxxxxxxxxxxxx
Link: alpine.DEB.2.20.1801031949200.1957@nanos">https://lkml.kernel.org/r/alpine.DEB.2.20.1801031949200.1957@nanos

---
 arch/x86/entry/entry_64_compat.S | 13 ++++++-------
 1 file changed, 6 insertions(+), 7 deletions(-)

diff --git a/arch/x86/entry/entry_64_compat.S b/arch/x86/entry/entry_64_compat.S
index 40f1700..98d5358 100644
--- a/arch/x86/entry/entry_64_compat.S
+++ b/arch/x86/entry/entry_64_compat.S
@@ -190,8 +190,13 @@ ENTRY(entry_SYSCALL_compat)
 	/* Interrupts are off on entry. */
 	swapgs
 
-	/* Stash user ESP and switch to the kernel stack. */
+	/* Stash user ESP */
 	movl	%esp, %r8d
+
+	/* Use %rsp as scratch reg. User ESP is stashed in r8 */
+	SWITCH_TO_KERNEL_CR3 scratch_reg=%rsp
+
+	/* Switch to the kernel stack */
 	movq	PER_CPU_VAR(cpu_current_top_of_stack), %rsp
 
 	/* Construct struct pt_regs on stack */
@@ -220,12 +225,6 @@ GLOBAL(entry_SYSCALL_compat_after_hwframe)
 	pushq   $0			/* pt_regs->r15 = 0 */
 
 	/*
-	 * We just saved %rdi so it is safe to clobber.  It is not
-	 * preserved during the C calls inside TRACE_IRQS_OFF anyway.
-	 */
-	SWITCH_TO_KERNEL_CR3 scratch_reg=%rdi
-
-	/*
 	 * User mode is traced as though IRQs are on, and SYSENTER
 	 * turned them off.
 	 */