Re: [PATCH] x86/acpi/cstate delete some unuseful operations

[Rafael J. Wysocki]

On Friday, December 22, 2017 12:55:04 PM CET TimGuo wrote:
> Unuseful cache flush operations which will be executed by ucode when entering C3 will
> cause larger C3 enter latency. And the bus master disable operation is not need for
> centaur platforms.

My attempts to make some sense of the above hoplessly failed. :-/

I understood that it was not necessary to disable bus master arbitration on C3
entry for Centaur CPUs, which is why you clear bm_control, right?

And the goal is to reduce the C3 latency, but I'm not sure about the cache
flushing part.  Do you want to say that disabling bus master arbitration causes
the CPU caches to be flushed which is time-consuming and should better be avoided
if not necessary?

> Signed-off-by: TimGuo <timguo@xxxxxxxxxxx>
> ---
>  arch/x86/kernel/acpi/cstate.c | 12 ++++++++++++
>  1 file changed, 12 insertions(+)
> 
> diff --git a/arch/x86/kernel/acpi/cstate.c b/arch/x86/kernel/acpi/cstate.c
> index dde437f..3eee490 100644
> --- a/arch/x86/kernel/acpi/cstate.c
> +++ b/arch/x86/kernel/acpi/cstate.c
> @@ -51,6 +51,18 @@ void acpi_processor_power_init_bm_check(struct acpi_processor_flags *flags,
>         if (c->x86_vendor == X86_VENDOR_INTEL &&
>             (c->x86 > 0xf || (c->x86 == 6 && c->x86_model >= 0x0f)))
>                         flags->bm_control = 0;
> +
> +       if (c->x86_vendor == X86_VENDOR_CENTAUR) {
> +               /*
> +                * on all centaur CPUs, sw need not execute cache flush operation
> +                * when entering C3 type state.
> +                *
> +                * On all Centaur platforms, ARB_DISABLE is not required while
> +                * entering C3 type state.
> +                */
> +               flags->bm_check = 1;
> +               flags->bm_control = 0;
> +        }
>  }
>  EXPORT_SYMBOL(acpi_processor_power_init_bm_check);
> 
> --
> 1.9.1
> 
> 
> 
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