Re: [PATCH 0/7] IBRS patch series

[Yves-Alexis Perez]

On Fri, 2018-01-05 at 15:26 +0100, Paolo Bonzini wrote:
> Those from November seem way too early to include IBRS/IBPB.  Maybe the
> two from December 3rd, but I wouldn't be 100% sure.

So, for my CPU with updated microcode:

processor	: 0
vendor_id	: GenuineIntel
cpu family	: 6
model		: 61
model name	: Intel(R) Core(TM) i5-5200U CPU @ 2.20GHz
stepping	: 4
microcode	: 0x28

cpuid returns:

   0x00000007 0x00: eax=0x00000000 ebx=0x021c27ab ecx=0x00000000
edx=0x0c000000

So bit 26/27 are set, which as I understand means IBRS is supported (but I
would appreciate any pointer to relevant documentation on this).
> 
> So it would be even nicer to know how those microcode updates were tested.

At least I didn't test IBRS/IBPB here. I could do it provided I'm pointed to a
tree with all the things to test.
> 
> (And by the way, the LFENCE change is for variant 1 aka CVE-2017-5753).

Ok, good to know. Is the kernel support part for LFENCE in the same thread (I
have to admit I'm a bit lost).

Regards,
-- 
Yves-Alexis

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