Re: [PATCH] 8250_dw: do not int overflow when rate can not be aplied

[Ed Blake]

On 11/01/18 17:55, Nuno GonÃalves wrote:
> So, for me clk_round_rate() always returns 24000000, and only the loop
> variable i changes, so the search is monotonic, from the highest baud
> to the lowest (increasing divider).
>
> I am using a Allwiner H2+, with the serial port configuration from
> sunxi-h3-h5.dtsi.
>
> Are you sure that clk_round_rate can return differet values? Is that
> because some boards might have several clock options beside the
> adjustable divider?

Yes I'm sure. Some platforms allow the clock rate to be varied, hence
the existence of clk_round_rate() and clk_set_rate().

> I really need to understand what is the problem, to be able to suggest
> a solution to the integer overflow that is being allowed to happen.

Some sort of overflow check on i * max_rate could work?

> Thanks,
> Nuno