Re: [PATCH 0/4] Add support for Intel IOMMU 5-level paging

[Joerg Roedel]

On Wed, Dec 20, 2017 at 11:59:23AM -0800, Sohil Mehta wrote:
> Sohil Mehta (4):
>   iommu/vt-d: Enable upto 57 bits of domain address width
>   iommu/vt-d: Add a check for 1GB page support
>   iommu/vt-d: Add a check for 5-level paging support
>   iommu/vt-d: Enable 5-level paging mode in the PASID entry
> 
>  drivers/iommu/intel-iommu.c |  2 +-
>  drivers/iommu/intel-svm.c   | 23 +++++++++++++++++++++--
>  include/linux/intel-iommu.h |  2 ++
>  3 files changed, 24 insertions(+), 3 deletions(-)

Applied, thanks.