Re: [PATCH v2 5/5] x86/pti: Do not enable PTI on fixed Intel processors

[David Woodhouse]

On Tue, 2018-01-23 at 10:12 -0800, Andi Kleen wrote:
> > -ÂÂÂÂÂif (c->x86_vendor != X86_VENDOR_AMD)
> > -ÂÂÂÂÂÂÂÂÂÂÂÂÂsetup_force_cpu_bug(X86_BUG_CPU_MELTDOWN);
> > +ÂÂÂÂÂif (c->x86_vendor != X86_VENDOR_AMD) {
> > +ÂÂÂÂÂÂÂÂÂÂÂÂÂu64 ia32_cap = 0;
> > +
> > +ÂÂÂÂÂÂÂÂÂÂÂÂÂif (cpu_has(c, X86_FEATURE_ARCH_CAPABILITIES))
> > +ÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂrdmsrl(MSR_IA32_ARCH_CAPABILITIES, ia32_cap);
> > +ÂÂÂÂÂÂÂÂÂÂÂÂÂif (!(ia32_cap & ARCH_CAP_RDCL_NO))
> > +ÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂsetup_force_cpu_bug(X86_BUG_CPU_MELTDOWN);
> 
> This means that in a hypervisor which passes through the CPUID,
> but actually doesn't implement the MSR (so rdmsr #GPs and returns 0)
> it would be cleared.Â
> 
> It would be better to usr rdmsrl_safe and check the return value.

This particular CPUID bit exists *purely* to advertise that the
IA32_ARCH_CAPABILITIES MSR exists. Nothing else. A hypervisor which
tells us the MSR exists and then doesn't expose it is fairly broken.
Not that it won't happen, of course.

But reading zero is fine. If the bit isn't set we do set the MELTDOWN
bug flag.

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