Re: asm-generic: Disallow no-op mb() for SMP systems

[Peter Zijlstra]

On Thu, Feb 01, 2018 at 09:27:50PM +0900, Stafford Horne wrote:
> I tried to clarify some of this in the spec v1.2 [0] which help formalize some of
> the techniques we used for the SMP implementation.  Its probably not perfect,
> but I added a section "10. Multicore support" and tried to clarify some things
> in section 7 on Atomicity.  But it seems I dont cover exactly what are are
> mentioning here.  In general:
> 
>   1 Secondary cores have memory snooping enabled meaning that any write to a
>     cached address will cause the cache line to be invalidated.
>   2 l.swa (store atomic word) implies a store buffer flush.

What about l.lwa? Can that observe 'old' values, or rather, miss values
stuck in a remote store buffer?

This will then cause the first l.swa to fail, which, per the above,
would then sync things up? Which means you get that one extra
merry-go-round.

>   3 l.msync is used to flush the store buffer
> 
> Also, during the IPI controller review [1] Marc Z asked many similar questions.
> I believe he was ok in the end.
> 
> Anyway,
> Thanks for thanks for spotting the issue here.  For some reason I remember we
> did have an l.msync for our mb().  Let me think about and test out this patch
> (and the fix to actually define mb) to see if anything comes up.
> 
> Also, I haven't seen any implementations that use WOM.  Stefan might know better.

So if the strong model has a store buffer, as I think the above says,
then it is _NOT_ correct for l.msync to be treated as a NOP, it _must_
flush the store buffer.

At which point I think your 'strong' model is basically TSO. So it would
be very good to get that spelled out somewhere.