[PATCH 3.16 047/136] clk: tegra: Fix cclk_lp divisor register

[Ben Hutchings]

3.16.54-rc1 review patch.  If anyone has any objections, please let me know.

------------------

From: MichaÅ MirosÅaw <mirq-linux@xxxxxxxxxxxx>

commit 54eff2264d3e9fd7e3987de1d7eba1d3581c631e upstream.

According to comments in code and common sense, cclk_lp uses its
own divisor, not cclk_g's.

Fixes: b08e8c0ecc42 ("clk: tegra: add clock support for Tegra30")
Signed-off-by: MichaÅ MirosÅaw <mirq-linux@xxxxxxxxxxxx>
Acked-By: Peter De Schrijver <pdeschrijver@xxxxxxxxxx>
Signed-off-by: Thierry Reding <treding@xxxxxxxxxx>
Signed-off-by: Ben Hutchings <ben@xxxxxxxxxxxxxxx>
---
 drivers/clk/tegra/clk-tegra30.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

--- a/drivers/clk/tegra/clk-tegra30.c
+++ b/drivers/clk/tegra/clk-tegra30.c
@@ -1060,7 +1060,7 @@ static void __init tegra30_super_clk_ini
 	 * U71 divider of cclk_lp.
 	 */
 	clk = tegra_clk_register_divider("pll_p_out3_cclklp", "pll_p_out3",
-				clk_base + SUPER_CCLKG_DIVIDER, 0,
+				clk_base + SUPER_CCLKLP_DIVIDER, 0,
 				TEGRA_DIVIDER_INT, 16, 8, 1, NULL);
 	clk_register_clkdev(clk, "pll_p_out3_cclklp", NULL);