Re: [PATCH v4 11/24] fpga: dfl: fme: add header sub feature support

[Alan Tull]

On Tue, Feb 13, 2018 at 3:24 AM, Wu Hao <hao.wu@xxxxxxxxx> wrote:

Hi Hao,

Looks good.

> From: Kang Luwei <luwei.kang@xxxxxxxxx>
>
> The Header Register set is always present for FPGA Management Engine (FME),
> this patch implements init and uinit function for header sub feature and
> introduce several read-only sysfs interfaces for the capability and status.
>
> Sysfs interfaces:
> * /sys/class/fpga_region/<regionX>/<dfl-fme.x>/ports_num
>   Read-only. Number of ports implemented
>
> * /sys/class/fpga_region/<regionX>/<dfl-fme.x>/bitstream_id
>   Read-only. Blue Bitstream (static FPGA region) identifier number. It contains
>   the detailed version and other information of this static FPGA region.
>
> * /sys/class/fpga_region/<regionX>/<dfl-fme.x>/bitstream_metadata
>   Read-only. Blue Bitstream (static FPGA region) meta data. It contains the
>   synthesis date, seed and other information of this static FPGA region.
>
> Signed-off-by: Tim Whisonant <tim.whisonant@xxxxxxxxx>
> Signed-off-by: Enno Luebbers <enno.luebbers@xxxxxxxxx>
> Signed-off-by: Shiva Rao <shiva.rao@xxxxxxxxx>
> Signed-off-by: Christopher Rauer <christopher.rauer@xxxxxxxxx>
> Signed-off-by: Kang Luwei <luwei.kang@xxxxxxxxx>
> Signed-off-by: Xiao Guangrong <guangrong.xiao@xxxxxxxxxxxxxxx>
> Signed-off-by: Wu Hao <hao.wu@xxxxxxxxx>
Acked-by: Alan Tull <atull@xxxxxxxxxx>

Thanks,
Alan