[PATCH v10 1/3] NPCM750: add clock controller to DT
From: Tali Perry
Date: Sun Feb 25 2018 - 05:15:49 EST
Signed-off-by: Tali Perry <tali.perry1@xxxxxxxxx>
---
arch/arm/boot/dts/nuvoton-npcm750.dtsi | 1221 ++++++++++++++++++++++++++++++++
1 file changed, 1221 insertions(+)
create mode 100644 arch/arm/boot/dts/nuvoton-npcm750.dtsi
diff --git a/arch/arm/boot/dts/nuvoton-npcm750.dtsi b/arch/arm/boot/dts/nuvoton-npcm750.dtsi
new file mode 100644
index 000000000000..a44a37c01972
--- /dev/null
+++ b/arch/arm/boot/dts/nuvoton-npcm750.dtsi
@@ -0,0 +1,1221 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * DTSi file for the NPCM750 SoC
+ *
+ * Copyright (c) 2014-2018 Nuvoton Technology corporation.
+ *
+ */
+
+#include "skeleton.dtsi"
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/clock/nuvoton,npcm7xx-clock.h>
+
+/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ interrupt-parent = <&gic>;
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ enable-method = "nuvoton,npcm7xx-smp";
+
+ cpu@0 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a9";
+ clocks = <&clk NPCM7XX_CLK_CPU>;
+ clock-names = "clk_cpu";
+ reg = <0>;
+ next-level-cache = <&l2>;
+ };
+
+ cpu@1 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a9";
+ clocks = <&clk NPCM7XX_CLK_CPU>;
+ clock-names = "clk_cpu";
+ reg = <1>;
+ next-level-cache = <&l2>;
+ };
+ };
+
+ gcr: gcr@f0800000 {
+ compatible = "nuvoton,npcm750-gcr", "syscon", "simple-mfd";
+ reg = <0xf0800000 0x1000>;
+ };
+
+ rst: rst@f0801000 {
+ compatible = "nuvoton,npcm750-rst", "syscon", "simple-mfd";
+ reg = <0xf0801000 0x1000>;
+ };
+
+ scu: scu@f03fe000 {
+ compatible = "arm,cortex-a9-scu";
+ reg = <0xf03fe000 0x1000>;
+ };
+
+ l2: cache-controller@f03fc000 {
+ compatible = "arm,pl310-cache";
+ reg = <0xf03fc000 0x1000>;
+ interrupts = <0 21 4>;
+ cache-unified;
+ arm,shared-override;
+ cache-level = <2>;
+ clocks = <&clk NPCM7XX_CLK_AXI>;
+ };
+
+ gic: interrupt-controller@f03ff000 {
+ compatible = "arm,cortex-a9-gic";
+ interrupt-controller;
+ #interrupt-cells = <3>;
+ reg = <0xf03ff000 0x1000>,
+ <0xf03fe100 0x100>;
+ };
+
+ timer@f03fe600 {
+ compatible = "arm,cortex-a9-twd-timer";
+ reg = <0xf03fe600 0x20>;
+ interrupts = <1 13 0x304>;
+ clocks = <&clk NPCM7XX_CLK_AHB>;
+ clock-names = "clk_ahb";
+ };
+
+
+ clk: clock-controller@f0801000 {
+ compatible = "nuvoton,npcm750-clk", "syscon";
+ #clock-cells = <1>;
+ clock-controller;
+ reg = <0xf0801000 0x1000>;
+ clock-names = "refclk", "sysbypck", "mcbypck";
+ clocks = <&clk_refclk>, <&clk_sysbypck>, <&clk_mcbypck>;
+ };
+
+ /* external reference clock */
+ clk_refclk: clk-refclk {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <25000000>;
+ clock-output-names = "refclk";
+ };
+
+ /* external reference clock for cpu. float in normal operation */
+ clk_sysbypck: clk-sysbypck {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <800000000>;
+ clock-output-names = "sysbypck";
+ };
+
+ /* external reference clock for MC. float in normal operation */
+ clk_mcbypck: clk-mcbypck {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <800000000>;
+ clock-output-names = "mcbypck";
+ };
+
+ /* external clock signal rg1refck, supplied by the phy */
+ clk_rg1refck: clk-rg1refck {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <125000000>;
+ clock-output-names = "clk_rg1refck";
+ };
+
+ /* external clock signal rg2refck, supplied by the phy */
+ clk_rg2refck: clk-rg2refck {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <125000000>;
+ clock-output-names = "clk_rg2refck";
+ };
+
+ clk_xin: clk-xin {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <50000000>;
+ clock-output-names = "clk_xin";
+ };
+
+
+ ahb {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "simple-bus";
+ interrupt-parent = <&gic>;
+ ranges = <0x80000000 0x80000000 0x40000000
+ 0xc0000000 0xc0000000 0x00002000
+ 0xc0008000 0xc0008000 0x00001000
+ 0xe0800000 0xe0800000 0x00001000
+ 0xe1000000 0xe1000000 0x00001000
+ 0xe8000000 0xe8000000 0x08000000
+ /* APB start */
+ 0xf0000000 0xf0000000 0x00005000
+ 0xf0007000 0xf0007000 0x00005000
+ 0xf0010000 0xf0010000 0x00008000
+ 0xf0080000 0xf0080000 0x00010000
+ 0xf009f000 0xf009f000 0x00001000
+ 0xf0100000 0xf0100000 0x00005000
+ 0xf0180000 0xf0180000 0x0000b000
+ 0xf0200000 0xf0200000 0x00002000
+ /* APB end */
+ 0xf0800000 0xf0800000 0x000fc000
+ 0xf8000000 0xf8000000 0x02000000
+ 0xfb000000 0xfb000000 0x00002000
+ 0xfffd0000 0xfffd0000 0x00005000>;
+
+ gmac0: eth@f0802000 {
+ device_type = "network";
+ compatible = "snps,dwmac";
+ reg = <0xf0802000 0x2000>;
+ interrupts = <0 14 4>;
+ interrupt-names = "macirq";
+ ethernet = <0>;
+ clocks = <&clk_rg1refck>, <&clk NPCM7XX_CLK_AHB>;
+ clock-names = "stmmaceth", "clk_gmac";
+ status = "disabled";
+ };
+
+ gmac1: eth@f0804000 {
+ device_type = "network";
+ compatible = "snps,dwmac";
+ reg = <0xf0804000 0x2000>;
+ interrupts = <0 17 4>;
+ interrupt-names = "macirq";
+ ethernet = <1>;
+ clocks = <&clk_rg2refck>, <&clk NPCM7XX_CLK_AHB>;
+ clock-names = "stmmaceth", "clk_gmac";
+ status = "disabled";
+ };
+
+ emc0: eth@f0825000 {
+ device_type = "network";
+ compatible = "nuvoton,npcm750-emc";
+ reg = <0xf0825000 0x1000>;
+ interrupts = <0 16 4>, <0 15 4>;
+ clocks = <&clk NPCM7XX_CLK_AHB>;
+ clock-names = "clk_emc";
+ };
+
+ emc1: eth@f0826000 {
+ device_type = "network";
+ compatible = "nuvoton,npcm750-emc";
+ reg = <0xf0826000 0x1000>;
+ interrupts = <0 115 4>, <0 114 4>;
+ clocks = <&clk NPCM7XX_CLK_AHB>;
+ clock-names = "clk_emc";
+ };
+
+ sdhci0: sdhci@f0840000 {
+ compatible = "nuvoton,npcm750-sdhci";
+ status = "disabled";
+ reg = <0xf0840000 0x200>;
+ interrupts = <0 27 4>;
+ clocks = <&clk NPCM7XX_CLK_AHB>; /*, <&clk_xin>;*/
+ clock-names = "clk_sdhc"; /* ,"clk_xin"; */
+ };
+
+ sdhci1: sdhci@f0842000 {
+ compatible = "nuvoton,npcm750-sdhci";
+ status = "disabled";
+ reg = <0xf0842000 0x200>;
+ interrupts = <0 26 4>;
+ clocks = <&clk NPCM7XX_CLK_AHB>; /*, <&clk_xin>;*/
+ clock-names = "clk_mmc"; /* ,"clk_xin"; */
+ };
+
+ ehci1:ehci@f0806000 {
+ compatible = "nuvoton,npcm750-ehci";
+ reg = <0xf0806000 0x1000>;
+ interrupts = <0 61 4>;
+ status = "disabled";
+ };
+
+ ohci1: ohci@f0807000 {
+ compatible = "nuvoton,npcm750-ohci";
+ reg = <0xf0807000 0x1000>;
+ interrupts = <0 62 4>;
+ status = "disabled";
+ };
+
+ udc0:udc@f0830000 {
+ compatible = "nuvoton,npcm750-udc";
+ reg = <0xf0830000 0x1000
+ 0xfffd0000 0x800>;
+ interrupts = <0 51 4>;
+ status = "disabled";
+ clocks = <&clk NPCM7XX_CLK_SU>;
+ clock-names = "clk_usb_bridge";
+ };
+
+ udc1:udc@f0831000 {
+ compatible = "nuvoton,npcm750-udc";
+ reg = <0xf0831000 0x1000
+ 0xfffd0800 0x800>;
+ interrupts = <0 52 4>;
+ status = "disabled";
+ clocks = <&clk NPCM7XX_CLK_SU>;
+ clock-names = "clk_usb_bridge";
+ };
+
+ udc2:udc@f0832000 {
+ compatible = "nuvoton,npcm750-udc";
+ reg = <0xf0832000 0x1000
+ 0xfffd1000 0x800>;
+ interrupts = <0 53 4>;
+ status = "disabled";
+ clocks = <&clk NPCM7XX_CLK_SU>;
+ clock-names = "clk_usb_bridge";
+ };
+
+ udc3:udc@f0833000 {
+ compatible = "nuvoton,npcm750-udc";
+ reg = <0xf0833000 0x1000
+ 0xfffd1800 0x800>;
+ interrupts = <0 54 4>;
+ status = "disabled";
+ clocks = <&clk NPCM7XX_CLK_SU>;
+ clock-names = "clk_usb_bridge";
+ };
+
+ udc4:udc@f0834000 {
+ compatible = "nuvoton,npcm750-udc";
+ reg = <0xf0834000 0x1000
+ 0xfffd2000 0x800>;
+ interrupts = <0 55 4>;
+ status = "disabled";
+ clocks = <&clk NPCM7XX_CLK_SU>;
+ clock-names = "clk_usb_bridge";
+ };
+
+ udc5:udc@f0835000 {
+ compatible = "nuvoton,npcm750-udc";
+ reg = <0xf0835000 0x1000
+ 0xfffd2800 0x800>;
+ interrupts = <0 56 4>;
+ status = "disabled";
+ clocks = <&clk NPCM7XX_CLK_SU>;
+ clock-names = "clk_usb_bridge";
+ };
+
+ udc6:udc@f0836000 {
+ compatible = "nuvoton,npcm750-udc";
+ reg = <0xf0836000 0x1000
+ 0xfffd3000 0x800>;
+ interrupts = <0 57 4>;
+ status = "disabled";
+ clocks = <&clk NPCM7XX_CLK_SU>;
+ clock-names = "clk_usb_bridge";
+ };
+
+ udc7:udc@f0837000 {
+ compatible = "nuvoton,npcm750-udc";
+ reg = <0xf0837000 0x1000
+ 0xfffd3800 0x800>;
+ interrupts = <0 58 4>;
+ status = "disabled";
+ clocks = <&clk NPCM7XX_CLK_SU>;
+ clock-names = "clk_usb_bridge";
+ };
+
+ udc8:udc@f0838000 {
+ compatible = "nuvoton,npcm750-udc";
+ reg = <0xf0838000 0x1000
+ 0xfffd4000 0x800>;
+ interrupts = <0 59 4>;
+ status = "disabled";
+ clocks = <&clk NPCM7XX_CLK_SU>;
+ clock-names = "clk_usb_bridge";
+ };
+
+ udc9:udc@f0839000 {
+ compatible = "nuvoton,npcm750-udc";
+ reg = <0xf0839000 0x1000
+ 0xfffd4800 0x800>;
+ interrupts = <0 60 4>;
+ status = "disabled";
+ clocks = <&clk NPCM7XX_CLK_SU>;
+ clock-names = "clk_usb_bridge";
+ };
+
+ aes:aes@f0858000 {
+ compatible = "nuvoton,npcm750-aes";
+ reg = <0xf0858000 0x1000>;
+ status = "disabled";
+ clocks = <&clk NPCM7XX_CLK_AHB>;
+ clock-names = "clk_ahb";
+ };
+
+ sha:sha@f085a000 {
+ compatible = "nuvoton,npcm750-sha";
+ reg = <0xf085a000 0x1000>;
+ status = "disabled";
+ clocks = <&clk NPCM7XX_CLK_AHB>;
+ clock-names = "clk_ahb";
+ };
+
+ copr: copr@0 {
+ compatible = "nuvoton,npcm750-copr";
+ interrupts = <0 1 4>;
+ clocks = <&clk NPCM7XX_CLK_AHB>;
+ clock-names = "clk_ahb";
+ };
+
+ vdma: vdma@e0800000 {
+ compatible = "nuvoton,npcm750-vdm";
+ reg = <0xe0800000 0x1000
+ 0xf0822000 0x1000>;
+ interrupts = <0 29 4>;
+ };
+
+ spi0: spi@fb000000 {
+ compatible = "nuvoton,npcm750-spi";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0xfb000000 0x1000>, <0x80000000 0x10000000>;
+ reg-names = "control", "memory";
+ chip-max-address-map = <0x8000000>;
+ clocks = <&clk NPCM7XX_CLK_AHB>;
+ clock-names = "clk_ahb";
+ spi-nor@0 {
+ compatible = "jedec,spi-nor";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ reg = <0>;
+ };
+ };
+ spi3: spi@c0000000 {
+ compatible = "nuvoton,npcm750-spi";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0xc0000000 0x1000>, <0xA0000000 0x20000000>;
+ reg-names = "control", "memory";
+ chip-max-address-map = <0x8000000>;
+ clocks = <&clk NPCM7XX_CLK_AHB>;
+ clock-names = "clk_ahb";
+ spi-nor@0 {
+ compatible = "jedec,spi-nor";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ reg = <0>;
+ };
+ };
+
+ pci_rc: axi-pcie@E1000000 {
+ #address-cells = <3>;
+ #size-cells = <2>;
+ #interrupt-cells = <1>;
+ compatible = "nuvoton,npcm750-pcirc";
+ reg = < 0xE1000000 0x1000 >;
+ device_type = "pci";
+ interrupts = < 0 127 4 >;
+ bus-range = <0x00 0xff>;
+ ranges = <0x02000000 0 0xEA000000
+ 0xEA000000 0 0x02000000>;
+ status = "disabled";
+ };
+
+ dvc: dvc@f0808000 {
+ compatible = "nuvoton,npcm750-dvc";
+ reg = <0xf0808000 0x1000>;
+ interrupts = <0 23 4>;
+ };
+
+ vcd: vcd@0 {
+ compatible = "nuvoton,npcm750-vcd";
+ reg = <0xf0810000 0x10000
+ 0xf0820000 0x2000>;
+ interrupts = <0 22 4>, <0 24 4>;
+ };
+
+ pcimbx: pcimbx@f0848000 {
+ compatible = "nuvoton,npcm750-pcimbx";
+ reg = <0xf0848000 0x10000>;
+ interrupts = <0 8 4>;
+ };
+ };
+
+ apb {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "simple-bus";
+ interrupt-parent = <&gic>;
+ ranges = <0xf0000000 0xf0000000 0x00005000
+ 0xf0007000 0xf0007000 0x00009000
+ 0xf0010000 0xf0010000 0x00008000
+ 0xf0080000 0xf0080000 0x00010000
+ 0xf009f000 0xf009f000 0x00001000
+ 0xf0100000 0xf0100000 0x00005000
+ 0xf0180000 0xf0180000 0x0000b000
+ 0xf0200000 0xf0200000 0x00002000>;
+
+ kcs: kcs@f0007000 {
+ compatible = "nuvoton,npcm750-kcs";
+ reg = <0xf0007000 0x1000>;
+ interrupts = <0 9 4>;
+ };
+
+ pspi: pspi@0 {
+ compatible = "nuvoton,npcm750-pspi";
+ reg = <0xf0200000 0x2000>;
+ interrupts = <0 31 4>, <0 28 4>;
+ clocks = <&clk NPCM7XX_CLK_APB5>;
+ clock-names = "clk_apb5";
+ };
+
+ fan: fan@0 {
+ compatible = "nuvoton,npcm750-fan";
+ reg = <0xf0180000 0x8000>;
+ interrupts = <0 96 4>, <0 97 4>, <0 98 4>, <0 99 4>,
+ <0 100 4>, <0 101 4>, <0 102 4>, <0 103 4>;
+ clocks = <&clk NPCM7XX_CLK_APB4>;
+ clock-names = "clk_apb4";
+ };
+
+ gpio: gpio@f0010000 {
+ compatible = "nuvoton,npcm750-gpio";
+ reg = <0xf0010000 0x8000>;
+ interrupts = <0 116 4>, <0 117 4>, <0 118 4>, <0 119 4>,
+ <0 120 4>, <0 121 4>, <0 122 4>, <0 123 4>;
+ clocks = <&clk NPCM7XX_CLK_APB1>;
+ clock-names = "clk_apb1";
+ };
+
+ timer0: timer@f0008000 {
+ compatible = "nuvoton,npcm750-timer";
+ interrupts = <0 32 4>;
+ reg = <0xf0008000 0x1000>;
+ clocks = <&clk NPCM7XX_CLK_TIMER>;
+ };
+
+ watchdog0: watchdog@f0008000 {
+ compatible = "nuvoton,npcm750-wdt";
+ interrupts = <0 47 4>;
+ reg = <0xf0008000 0x1000>;
+ status = "disabled";
+ clocks = <&clk NPCM7XX_CLK_TIMER>;
+ };
+
+ watchdog1: watchdog@f0009000 {
+ compatible = "nuvoton,npcm750-wdt";
+ interrupts = <0 48 4>;
+ reg = <0xf0009000 0x1000>;
+ status = "disabled";
+ clocks = <&clk NPCM7XX_CLK_TIMER>;
+ };
+
+ watchdog2: watchdog@f000a000 {
+ compatible = "nuvoton,npcm750-wdt";
+ interrupts = <0 49 4>;
+ reg = <0xf000a000 0x1000>;
+ status = "disabled";
+ clocks = <&clk NPCM7XX_CLK_TIMER>;
+ };
+
+ serial0: serial0@f0001000 {
+ compatible = "nuvoton,npcm750-uart";
+ reg = <0xf0001000 0x1000>;
+ clocks = <&clk NPCM7XX_CLK_UART>;
+ reg-shift = <2>;
+ fifo-size = <14>;
+ interrupts = <0 2 4>;
+ status = "disabled";
+ };
+
+ serial1: serial1@f0002000 {
+ compatible = "nuvoton,npcm750-uart";
+ reg = <0xf0002000 0x1000>;
+ clocks = <&clk NPCM7XX_CLK_UART>;
+ reg-shift = <2>;
+ fifo-size = <14>;
+ interrupts = <0 3 4>;
+ status = "disabled";
+ };
+
+ serial2: serial2@f0003000 {
+ compatible = "nuvoton,npcm750-uart";
+ reg = <0xf0003000 0x1000>;
+ clocks = <&clk NPCM7XX_CLK_UART>;
+ reg-shift = <2>;
+ fifo-size = <16>;
+ interrupts = <0 4 4>;
+ status = "disabled";
+ };
+
+ serial3: serial3@f0004000 {
+ compatible = "nuvoton,npcm750-uart";
+ reg = <0xf0004000 0x1000>;
+ clocks = <&clk NPCM7XX_CLK_UART>;
+ reg-shift = <2>;
+ fifo-size = <16>;
+ interrupts = <0 5 4>;
+ status = "disabled";
+ };
+
+ rng: rng@f000b000 {
+ compatible = "nuvoton,npcm750-rng";
+ reg = <0xf000b000 0x1000>;
+ clocks = <&clk NPCM7XX_CLK_APB1>;
+ clock-names = "clk_apb1";
+ status = "disabled";
+ };
+
+ adc: adc@f000c000 {
+ compatible = "nuvoton,npcm750-adc";
+ reg = <0xf000c000 0x1000>;
+ clocks = <&clk NPCM7XX_CLK_ADC>;
+ clock-names = "clk_adc";
+ vref = <2048>;
+ };
+
+ otp:otp@f0189000 {
+ compatible = "nuvoton,npcm750-otp";
+ reg = <0xf0189000 0x1000
+ 0xf018a000 0x1000>;
+ status = "disabled";
+ clocks = <&clk NPCM7XX_CLK_APB4>;
+ clock-names = "clk_apb4";
+ };
+
+ pwm:pwm@f0103000 {
+ compatible = "nuvoton,npcm750-pwm";
+ reg = <0xf0103000 0x1000
+ 0xf0104000 0x1000>;
+ clocks = <&clk NPCM7XX_CLK_APB3>;
+ clock-names = "clk_apb3";
+ };
+
+ i2c0: i2c-bus@f0080000 {
+ reg = <0xf0080000 0x1000>;
+ compatible = "nuvoton,npcm750-i2c-bus";
+ clocks = <&clk NPCM7XX_CLK_APB2>;
+ bus-frequency = <100000>;
+ interrupts = <0 64 4>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&smb0_pins>;
+ status = "disabled";
+ };
+ i2c1: i2c-bus@f0081000 {
+ reg = <0xf0081000 0x1000>;
+ compatible = "nuvoton,npcm750-i2c-bus";
+ clocks = <&clk NPCM7XX_CLK_APB2>;
+ bus-frequency = <100000>;
+ interrupts = <0 65 4>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&smb1_pins>;
+ status = "disabled";
+ };
+ i2c2: i2c-bus@f0082000 {
+ reg = <0xf0082000 0x1000>;
+ compatible = "nuvoton,npcm750-i2c-bus";
+ clocks = <&clk NPCM7XX_CLK_APB2>;
+ bus-frequency = <100000>;
+ interrupts = <0 66 4>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&smb2_pins>;
+ status = "disabled";
+ };
+ i2c3: i2c-bus@f0083000 {
+ reg = <0xf0083000 0x1000>;
+ compatible = "nuvoton,npcm750-i2c-bus";
+ clocks = <&clk NPCM7XX_CLK_APB2>;
+ bus-frequency = <100000>;
+ interrupts = <0 67 4>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&smb3_pins>;
+ status = "disabled";
+ };
+ i2c4: i2c-bus@f0084000 {
+ reg = <0xf0084000 0x1000>;
+ compatible = "nuvoton,npcm750-i2c-bus";
+ clocks = <&clk NPCM7XX_CLK_APB2>;
+ bus-frequency = <100000>;
+ interrupts = <0 68 4>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&smb4_pins>;
+ status = "disabled";
+ };
+ i2c5: i2c-bus@f0085000 {
+ reg = <0xf0085000 0x1000>;
+ compatible = "nuvoton,npcm750-i2c-bus";
+ clocks = <&clk NPCM7XX_CLK_APB2>;
+ bus-frequency = <100000>;
+ interrupts = <0 69 4>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&smb5_pins>;
+ status = "disabled";
+ };
+ i2c6: i2c-bus@f0086000 {
+ reg = <0xf0086000 0x1000>;
+ compatible = "nuvoton,npcm750-i2c-bus";
+ clocks = <&clk NPCM7XX_CLK_APB2>;
+ bus-frequency = <100000>;
+ interrupts = <0 70 4>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&smb6_pins>;
+ status = "disabled";
+ };
+ i2c7: i2c-bus@f0087000 {
+ reg = <0xf0087000 0x1000>;
+ compatible = "nuvoton,npcm750-i2c-bus";
+ clocks = <&clk NPCM7XX_CLK_APB2>;
+ bus-frequency = <100000>;
+ interrupts = <0 71 4>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&smb7_pins>;
+ status = "disabled";
+ };
+ i2c8: i2c-bus@f0088000 {
+ reg = <0xf0088000 0x1000>;
+ compatible = "nuvoton,npcm750-i2c-bus";
+ clocks = <&clk NPCM7XX_CLK_APB2>;
+ bus-frequency = <100000>;
+ interrupts = <0 72 4>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&smb8_pins>;
+ status = "disabled";
+ };
+ i2c9: i2c-bus@f0089000 {
+ reg = <0xf0089000 0x1000>;
+ compatible = "nuvoton,npcm750-i2c-bus";
+ clocks = <&clk NPCM7XX_CLK_APB2>;
+ bus-frequency = <100000>;
+ interrupts = <0 73 4>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&smb9_pins>;
+ status = "disabled";
+ };
+ i2c10: i2c-bus@f008a000 {
+ reg = <0xf008a000 0x1000>;
+ compatible = "nuvoton,npcm750-i2c-bus";
+ clocks = <&clk NPCM7XX_CLK_APB2>;
+ bus-frequency = <100000>;
+ interrupts = <0 74 4>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&smb10_pins>;
+ status = "disabled";
+ };
+ i2c11: i2c-bus@f008b000 {
+ reg = <0xf008b000 0x1000>;
+ compatible = "nuvoton,npcm750-i2c-bus";
+ clocks = <&clk NPCM7XX_CLK_APB2>;
+ bus-frequency = <100000>;
+ interrupts = <0 75 4>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&smb11_pins>;
+ status = "disabled";
+ };
+ i2c12: i2c-bus@f008c000 {
+ reg = <0xf008c000 0x1000>;
+ compatible = "nuvoton,npcm750-i2c-bus";
+ clocks = <&clk NPCM7XX_CLK_APB2>;
+ bus-frequency = <100000>;
+ interrupts = <0 76 4>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&smb12_pins>;
+ status = "disabled";
+ };
+ i2c13: i2c-bus@f008d000 {
+ reg = <0xf008d000 0x1000>;
+ compatible = "nuvoton,npcm750-i2c-bus";
+ clocks = <&clk NPCM7XX_CLK_APB2>;
+ bus-frequency = <100000>;
+ interrupts = <0 77 4>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&smb13_pins>;
+ status = "disabled";
+ };
+ i2c14: i2c-bus@f008e000 {
+ reg = <0xf008e000 0x1000>;
+ compatible = "nuvoton,npcm750-i2c-bus";
+ clocks = <&clk NPCM7XX_CLK_APB2>;
+ bus-frequency = <100000>;
+ interrupts = <0 78 4>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&smb14_pins>;
+ status = "disabled";
+ };
+ i2c15: i2c-bus@f008f000 {
+ reg = <0xf008f000 0x1000>;
+ compatible = "nuvoton,npcm750-i2c-bus";
+ clocks = <&clk NPCM7XX_CLK_APB2>;
+ bus-frequency = <100000>;
+ interrupts = <0 79 4>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&smb15_pins>;
+ status = "disabled";
+ };
+ };
+ pinctrl: pinctrl@0 {
+ compatible = "nuvoton,npcmx50-pinctrl";
+ status = "okay";
+ iox1_pins: iox1_pins {
+ groups = "iox1";
+ function = "iox1";
+ };
+ iox2_pins: iox2_pins {
+ groups = "iox2";
+ function = "iox2";
+ };
+ smb1d_pins: smb1d_pins {
+ groups = "smb1d";
+ function = "smb1d";
+ };
+ smb2d_pins: smb2d_pins {
+ groups = "smb2d";
+ function = "smb2d";
+ };
+ lkgpo1_pins: lkgpo1_pins {
+ groups = "lkgpo1";
+ function = "lkgpo1";
+ };
+ lkgpo2_pins: lkgpo2_pins {
+ groups = "lkgpo2";
+ function = "lkgpo2";
+ };
+ ioxh_pins: ioxh_pins {
+ groups = "ioxh";
+ function = "ioxh";
+ };
+ gspi_pins: gspi_pins {
+ groups = "gspi";
+ function = "gspi";
+ };
+ smb5b_pins: smb5b_pins {
+ groups = "smb5b";
+ function = "smb5b";
+ };
+ smb5c_pins: smb5c_pins {
+ groups = "smb5c";
+ function = "smb5c";
+ };
+ lkgpo0_pins: lkgpo0_pins {
+ groups = "lkgpo0";
+ function = "lkgpo0";
+ };
+ pspi2_pins: pspi2_pins {
+ groups = "pspi2";
+ function = "pspi2";
+ };
+ smb4den_pins: smb4den_pins {
+ groups = "smb4den";
+ function = "smb4den";
+ };
+ smb4b_pins: smb4b_pins {
+ groups = "smb4b";
+ function = "smb4b";
+ };
+ smb4c_pins: smb4c_pins {
+ groups = "smb4c";
+ function = "smb4c";
+ };
+ smb15_pins: smb15_pins {
+ groups = "smb15";
+ function = "smb15";
+ };
+ smb4d_pins: smb4d_pins {
+ groups = "smb4d";
+ function = "smb4d";
+ };
+ smb14_pins: smb14_pins {
+ groups = "smb14";
+ function = "smb14";
+ };
+ smb5_pins: smb5_pins {
+ groups = "smb5";
+ function = "smb5";
+ };
+ smb4_pins: smb4_pins {
+ groups = "smb4";
+ function = "smb4";
+ };
+ smb3_pins: smb3_pins {
+ groups = "smb3";
+ function = "smb3";
+ };
+ spi0cs1_pins: spi0cs1_pins {
+ groups = "spi0cs1";
+ function = "spi0cs1";
+ };
+ spi0quad_pins: spi0quad_pins {
+ groups = "spi0quad";
+ function = "spi0quad";
+ };
+ spi0cs2_pins: spi0cs2_pins {
+ groups = "spi0cs2";
+ function = "spi0cs2";
+ };
+ spi0cs3_pins: spi0cs3_pins {
+ groups = "spi0cs3";
+ function = "spi0cs3";
+ };
+ smb3c_pins: smb3c_pins {
+ groups = "smb3c";
+ function = "smb3c";
+ };
+ smb3b_pins: smb3b_pins {
+ groups = "smb3b";
+ function = "smb3b";
+ };
+ bmcuart0a_pins: bmcuart0a_pins {
+ groups = "bmcuart0a";
+ function = "bmcuart0a";
+ };
+ uart1_pins: uart1_pins {
+ groups = "uart1";
+ function = "uart1";
+ };
+ jtag2_pins: jtag2_pins {
+ groups = "jtag2";
+ function = "jtag2";
+ };
+ bmcuart1_pins: bmcuart1_pins {
+ groups = "bmcuart1";
+ function = "bmcuart1";
+ };
+ uart2_pins: uart2_pins {
+ groups = "uart2";
+ function = "uart2";
+ };
+ bmcuart0b_pins: bmcuart0b_pins {
+ groups = "bmcuart0b";
+ function = "bmcuart0b";
+ };
+ r1err_pins: r1err_pins {
+ groups = "r1err";
+ function = "r1err";
+ };
+ r1md_pins: r1md_pins {
+ groups = "r1md";
+ function = "r1md";
+ };
+ smb3d_pins: smb3d_pins {
+ groups = "smb3d";
+ function = "smb3d";
+ };
+ fanin0_pins: fanin0_pins {
+ groups = "fanin0";
+ function = "fanin0";
+ };
+ fanin1_pins: fanin1_pins {
+ groups = "fanin1";
+ function = "fanin1";
+ };
+ fanin2_pins: fanin2_pins {
+ groups = "fanin2";
+ function = "fanin2";
+ };
+ fanin3_pins: fanin3_pins {
+ groups = "fanin3";
+ function = "fanin3";
+ };
+ fanin4_pins: fanin4_pins {
+ groups = "fanin4";
+ function = "fanin4";
+ };
+ fanin5_pins: fanin5_pins {
+ groups = "fanin5";
+ function = "fanin5";
+ };
+ fanin6_pins: fanin6_pins {
+ groups = "fanin6";
+ function = "fanin6";
+ };
+ fanin7_pins: fanin7_pins {
+ groups = "fanin7";
+ function = "fanin7";
+ };
+ fanin8_pins: fanin8_pins {
+ groups = "fanin8";
+ function = "fanin8";
+ };
+ fanin9_pins: fanin9_pins {
+ groups = "fanin9";
+ function = "fanin9";
+ };
+ fanin10_pins: fanin10_pins {
+ groups = "fanin10";
+ function = "fanin10";
+ };
+ fanin11_pins: fanin11_pins {
+ groups = "fanin11";
+ function = "fanin11";
+ };
+ fanin12_pins: fanin12_pins {
+ groups = "fanin12";
+ function = "fanin12";
+ };
+ fanin13_pins: fanin13_pins {
+ groups = "fanin13";
+ function = "fanin13";
+ };
+ fanin14_pins: fanin14_pins {
+ groups = "fanin14";
+ function = "fanin14";
+ };
+ fanin15_pins: fanin15_pins {
+ groups = "fanin15";
+ function = "fanin15";
+ };
+ pwm0_pins: pwm0_pins {
+ groups = "pwm0";
+ function = "pwm0";
+ };
+ pwm1_pins: pwm1_pins {
+ groups = "pwm1";
+ function = "pwm1";
+ };
+ pwm2_pins: pwm2_pins {
+ groups = "pwm2";
+ function = "pwm2";
+ };
+ pwm3_pins: pwm3_pins {
+ groups = "pwm3";
+ function = "pwm3";
+ };
+ r2_pins: r2_pins {
+ groups = "r2";
+ function = "r2";
+ };
+ r2err_pins: r2err_pins {
+ groups = "r2err";
+ function = "r2err";
+ };
+ r2md_pins: r2md_pins {
+ groups = "r2md";
+ function = "r2md";
+ };
+ ga20kbc_pins: ga20kbc_pins {
+ groups = "ga20kbc";
+ function = "ga20kbc";
+ };
+ smb5d_pins: smb5d_pins {
+ groups = "smb5d";
+ function = "smb5d";
+ };
+ lpc_pins: lpc_pins {
+ groups = "lpc";
+ function = "lpc";
+ };
+ espi_pins: espi_pins {
+ groups = "espi";
+ function = "espi";
+ };
+ rg1_pins: rg1_pins {
+ groups = "rg1";
+ function = "rg1";
+ };
+ rg1mdio_pins: rg1mdio_pins {
+ groups = "rg1mdio";
+ function = "rg1mdio";
+ };
+ rg2_pins: rg2_pins {
+ groups = "rg2";
+ function = "rg2";
+ };
+ ddr_pins: ddr_pins {
+ groups = "ddr";
+ function = "ddr";
+ };
+ smb0_pins: smb0_pins {
+ groups = "smb0";
+ function = "smb0";
+ };
+ smb1_pins: smb1_pins {
+ groups = "smb1";
+ function = "smb1";
+ };
+ smb2_pins: smb2_pins {
+ groups = "smb2";
+ function = "smb2";
+ };
+ smb2c_pins: smb2c_pins {
+ groups = "smb2c";
+ function = "smb2c";
+ };
+ smb2b_pins: smb2b_pins {
+ groups = "smb2b";
+ function = "smb2b";
+ };
+ smb1c_pins: smb1c_pins {
+ groups = "smb1c";
+ function = "smb1c";
+ };
+ smb1b_pins: smb1b_pins {
+ groups = "smb1b";
+ function = "smb1b";
+ };
+ smb8_pins: smb8_pins {
+ groups = "smb8";
+ function = "smb8";
+ };
+ smb9_pins: smb9_pins {
+ groups = "smb9";
+ function = "smb9";
+ };
+ smb10_pins: smb10_pins {
+ groups = "smb10";
+ function = "smb10";
+ };
+ smb11_pins: smb11_pins {
+ groups = "smb11";
+ function = "smb11";
+ };
+ sd1_pins: sd1_pins {
+ groups = "sd1";
+ function = "sd1";
+ };
+ sd1pwr_pins: sd1pwr_pins {
+ groups = "sd1pwr";
+ function = "sd1pwr";
+ };
+ pwm4_pins: pwm4_pins {
+ groups = "pwm4";
+ function = "pwm4";
+ };
+ pwm5_pins: pwm5_pins {
+ groups = "pwm5";
+ function = "pwm5";
+ };
+ pwm6_pins: pwm6_pins {
+ groups = "pwm6";
+ function = "pwm6";
+ };
+ pwm7_pins: pwm7_pins {
+ groups = "pwm7";
+ function = "pwm7";
+ };
+ mmc8_pins: mmc8_pins {
+ groups = "mmc8";
+ function = "mmc8";
+ };
+ mmc_pins: mmc_pins {
+ groups = "mmc";
+ function = "mmc";
+ };
+ mmcwp_pins: mmcwp_pins {
+ groups = "mmcwp";
+ function = "mmcwp";
+ };
+ mmccd_pins: mmccd_pins {
+ groups = "mmccd";
+ function = "mmccd";
+ };
+ mmcrst_pins: mmcrst_pins {
+ groups = "mmcrst";
+ function = "mmcrst";
+ };
+ clkout_pins: clkout_pins {
+ groups = "clkout";
+ function = "clkout";
+ };
+ serirq_pins: serirq_pins {
+ groups = "serirq";
+ function = "serirq";
+ };
+ scipme_pins: scipme_pins {
+ groups = "scipme";
+ function = "scipme";
+ };
+ sci_pins: sci_pins {
+ groups = "sci";
+ function = "sci";
+ };
+ smb6_pins: smb6_pins {
+ groups = "smb6";
+ function = "smb6";
+ };
+ smb7_pins: smb7_pins {
+ groups = "smb7";
+ function = "smb7";
+ };
+ pspi1_pins: pspi1_pins {
+ groups = "pspi1";
+ function = "pspi1";
+ };
+ faninx_pins: faninx_pins {
+ groups = "faninx";
+ function = "faninx";
+ };
+ r1_pins: r1_pins {
+ groups = "r1";
+ function = "r1";
+ };
+ spi3_pins: spi3_pins {
+ groups = "spi3";
+ function = "spi3";
+ };
+ spi3cs1_pins: spi3cs1_pins {
+ groups = "spi3cs1";
+ function = "spi3cs1";
+ };
+ spi3quad_pins: spi3quad_pins {
+ groups = "spi3quad";
+ function = "spi3quad";
+ };
+ spi3cs2_pins: spi3cs2_pins {
+ groups = "spi3cs2";
+ function = "spi3cs2";
+ };
+ spi3cs3_pins: spi3cs3_pins {
+ groups = "spi3cs3";
+ function = "spi3cs3";
+ };
+ nprd_smi_pins: nprd_smi_pins {
+ groups = "nprd_smi";
+ function = "nprd_smi";
+ };
+ smb0b_pins: smb0b_pins {
+ groups = "smb0b";
+ function = "smb0b";
+ };
+ smb0c_pins: smb0c_pins {
+ groups = "smb0c";
+ function = "smb0c";
+ };
+ smb0den_pins: smb0den_pins {
+ groups = "smb0den";
+ function = "smb0den";
+ };
+ smb0d_pins: smb0d_pins {
+ groups = "smb0d";
+ function = "smb0d";
+ };
+ ddc_pins: ddc_pins {
+ groups = "ddc";
+ function = "ddc";
+ };
+ rg2mdio_pins: rg2mdio_pins {
+ groups = "rg2mdio";
+ function = "rg2mdio";
+ };
+ wdog1_pins: wdog1_pins {
+ groups = "wdog1";
+ function = "wdog1";
+ };
+ wdog2_pins: wdog2_pins {
+ groups = "wdog2";
+ function = "wdog2";
+ };
+ smb12_pins: smb12_pins {
+ groups = "smb12";
+ function = "smb12";
+ };
+ smb13_pins: smb13_pins {
+ groups = "smb13";
+ function = "smb13";
+ };
+ spix_pins: spix_pins {
+ groups = "spix";
+ function = "spix";
+ };
+ spixcs1_pins: spixcs1_pins {
+ groups = "spixcs1";
+ function = "spixcs1";
+ };
+ clkreq_pins: clkreq_pins {
+ groups = "clkreq";
+ function = "clkreq";
+ };
+ };
+};
--
2.14.1