Re: [PATCH 3.16 091/254] MIPS: CPS: Fix r1 .set mt assembler warning

[Ben Hutchings]

On Thu, 2018-03-01 at 13:44 +0000, James Hogan wrote:
> On Wed, Feb 28, 2018 at 03:20:18PM +0000, Ben Hutchings wrote:
> > 3.16.55-rc1 review patch.  If anyone has any objections, please let me know.
> > 
> > ------------------
> > 
> > From: James Hogan <jhogan@xxxxxxxxxx>
> > 
> > commit 17278a91e04f858155d54bee5528ba4fbcec6f87 upstream.
> 
> You'll want this too:
> 
> 8dbc1864b74f5dea5a3f7c30ca8fd358a675132f
> MIPS: CPS: Fix MIPS_ISA_LEVEL_RAW fallout
> 
> Its only tagged for stable 4.15 since the one it fixes wasn't tagged for
> stable.
> 
> If you're going to select patches for backporting based on Fixes tags,
> maybe its worth looking for patches which are marked as fixing ones
> you've backported too.

I do that, but didn't look beyond v4.15 yet.  Here's the version of
that fix I've ended up with for 3.16.

Ben.

-- 
Ben Hutchings
[W]e found...that it wasn't as easy to get programs right as we had
thought. ... I realized that a large part of my life from then on was
going to be spent in finding mistakes in my own programs. - Maurice
Wilkes, 1949

From: James Hogan <jhogan@xxxxxxxxxx>
Date: Fri, 2 Feb 2018 14:36:40 +0000
Subject: MIPS: CPS: Fix MIPS_ISA_LEVEL_RAW fallout

commit 8dbc1864b74f5dea5a3f7c30ca8fd358a675132f upstream.

Commit 17278a91e04f ("MIPS: CPS: Fix r1 .set mt assembler warning")
added .set MIPS_ISA_LEVEL_RAW to silence warnings about .set mt on r1,
however this can result in a MOVE being encoded as a 64-bit DADDU
instruction on certain version of binutils (e.g. 2.22), and reserved
instruction exceptions at runtime on 32-bit hardware.

Reduce the sizes of the push/pop sections to include only instructions
that are part of the MT ASE or which won't convert to 64-bit
instructions after .set mips64r2/mips64r6.

Reported-by: Greg Ungerer <gerg@xxxxxxxxxxxxxx>
Fixes: 17278a91e04f ("MIPS: CPS: Fix r1 .set mt assembler warning")
Signed-off-by: James Hogan <jhogan@xxxxxxxxxx>
Cc: Ralf Baechle <ralf@xxxxxxxxxxxxxx>
Cc: Paul Burton <paul.burton@xxxxxxxx>
Cc: linux-mips@xxxxxxxxxxxxxx
Tested-by: Greg Ungerer <gerg@xxxxxxxxxxxxxx>
Patchwork: https://patchwork.linux-mips.org/patch/18578/
[bwh: Backported to 3.16: adjust context]
Signed-off-by: Ben Hutchings <ben@xxxxxxxxxxxxxxx>
---
--- a/arch/mips/kernel/cps-vec.S
+++ b/arch/mips/kernel/cps-vec.S
@@ -347,12 +347,13 @@ LEAF(mips_cps_boot_vpes)
 	jr	ra
 	 nop
 
+1:	/* Enter VPE configuration state */
 	.set	push
 	.set	MIPS_ISA_LEVEL_RAW
 	.set	mt
-
-1:	/* Enter VPE configuration state */
 	dvpe
+	.set	pop
+
 	la	t1, 1f
 	jr.hb	t1
 	 nop
@@ -379,6 +380,10 @@ LEAF(mips_cps_boot_vpes)
 	mtc0	t0, CP0_VPECONTROL
 	ehb
 
+	.set	push
+	.set	MIPS_ISA_LEVEL_RAW
+	.set	mt
+
 	/* Skip the VPE if its TC is not halted */
 	mftc0	t0, CP0_TCHALT
 	beqz	t0, 2f
@@ -437,6 +442,8 @@ LEAF(mips_cps_boot_vpes)
 	ehb
 	evpe
 
+	.set	pop
+
 	/* Check whether this VPE is meant to be running */
 	li	t0, 1
 	sll	t0, t0, t9
@@ -451,7 +458,7 @@ LEAF(mips_cps_boot_vpes)
 1:	jr.hb	t0
 	 nop
 
-2:	.set	pop
+2:
 
 #endif /* CONFIG_MIPS_MT_SMP */

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