Re: [PATCH] perf vendor events arm64: Enable JSON events for ThunderX2 B0

[John Garry]

On 07/03/2018 14:38, Arnaldo Carvalho de Melo wrote:
> Em Wed, Mar 07, 2018 at 09:32:05AM -0500, William Cohen escreveu:
> > On 03/07/2018 06:08 AM, Ganapatrao Kulkarni wrote:
> > > There is MIDR change on ThunderX2 B0, adding an entry to mapfile
> > > to enable JSON events for B0.
> > >
> > > Signed-off-by: Ganapatrao Kulkarni <ganapatrao.kulkarni@xxxxxxxxxx>
>
> Ganapatrao, can you please take this in consideration and if agreeing
> send a v2 patch?
>
> With that I can add an Acked-by: wcohen, Right?

JFYI, This patch conflicts with "[PATCH v2 00/11] perf events patches 
for improved ARM64 support". I was planning on sending a v3 quite soon.

> - Arnaldo
> > > ---
> > >  tools/perf/pmu-events/arch/arm64/mapfile.csv | 1 +
> > >  1 file changed, 1 insertion(+)
> > >
> > > diff --git a/tools/perf/pmu-events/arch/arm64/mapfile.csv b/tools/perf/pmu-events/arch/arm64/mapfile.csv
> > > index e61c9ca..93c5d14 100644
> > > --- a/tools/perf/pmu-events/arch/arm64/mapfile.csv
> > > +++ b/tools/perf/pmu-events/arch/arm64/mapfile.csv
> > > @@ -13,4 +13,5 @@
> > >  #
> > >  #Family-model,Version,Filename,EventType
> > >  0x00000000420f5160,v1,cavium,core
> > > +0x00000000430f0af0,v1,cavium,core
> > >  0x00000000410fd03[[:xdigit:]],v1,cortex-a53,core
> >
> > Hi,
> > Like the cortex-a53 the last digit '0' of the match for the MIDR should be replaced with [[:xdigit:]] to allow for possible future revisions of chip:
> >
> > 0x00000000430f0af[[:xdigit:]],v1,cavium,core
> >
> >
> > -Will Cohen
>
> .

Thanks,
John

>