Re: [tip:x86/mm] x86/boot/compressed/64: Describe the logic behind the LA57 check

[Kirill A. Shutemov]

On Mon, Mar 12, 2018 at 02:32:12PM +0000, Ingo Molnar wrote:
> 
> * Kirill A. Shutemov <kirill@xxxxxxxxxxxxx> wrote:
> 
> > > We can of course bike shed / benchmark this once my desktop refresh
> > > sports this feature, but ISTR this being one of the very first things
> > > Ingo mentioned when we started this whole 5L thing.
> > 
> > I would rather not fix the problem that may not actually exist. :)
> 
> That 5 level pagetables involve more overhead is a realy problem.

As I mentioned before, microarchitecture changes takes care about
additional overhead: size of intermediate TLB was increased which should
make the difference between 4- and 5-level paging negligible.

> By default we should only enable 5-level paging if memory mappings exist in
> the memory map that require the extended physical memory space.

I disagree that we should decide usefulness of the 5-level paging based on
size of physical memory on the machine.

Consider use case when you have 100TiB database file. It's pretty
reasonable to mmap() such file at once even if you don't have 100TiB of
physical memory to back it up. 1/100 of the file size may still work
fairly well.

Virtual address space is useful on its own and we shouldn't take the
value from the user just because he doesn't have tens of terabytes of
memory.

-- 
 Kirill A. Shutemov