Re: [tip:x86/mm] x86/boot/compressed/64: Describe the logic behind the LA57 check

[Andy Lutomirski]

On Mon, Mar 12, 2018 at 4:42 PM, Linus Torvalds
<torvalds@xxxxxxxxxxxxxxxxxxxx> wrote:
> On Mon, Mar 12, 2018 at 7:50 AM, Kirill A. Shutemov
> <kirill.shutemov@xxxxxxxxxxxxxxx> wrote:
>>
>> I disagree that we should decide usefulness of the 5-level paging based on
>> size of physical memory on the machine.
>>
>> Consider use case when you have 100TiB database file. It's pretty
>> reasonable to mmap() such file at once even if you don't have 100TiB of
>> physical memory to back it up. 1/100 of the file size may still work
>> fairly well.
>>
>> Virtual address space is useful on its own and we shouldn't take the
>> value from the user just because he doesn't have tens of terabytes of
>> memory.
>
> Absolutely.
>
> Also, I'd suggest enabling 5-level paging as aggressively as possible
> by default (ie whenever the hardware supports it), just for test
> coverage.
>
> Maybe in a year or two, when we actually have a fair amount of
> coverage, we'll then say "ok, this just hurts normal workstations that
> have the capability but only have ridiculously small fraction of
> memory", and at that point say that unless you have a ton of RAM we'll
> default to 4-level.
>

I'd be surprised if there's a noticeable performance hit on anything
except the micro-est of benchmarks.  We're talking one extra
intermediate paging structure cache entry in use, maybe a few data
cache lines, and (wild guess) 0 extra cycles on a TLB miss in the
normal case.  This is because the walks are almost never going to
start at the root.

The real hit will be the extra page table for every task.