Re: [PATCH 1/1] x86/platform/x86: Fix count of CHas on multi-pci-segment arches

[Liang, Kan]

On 3/13/2018 1:22 PM, Andy Shevchenko wrote:
> On Tue, Mar 13, 2018 at 7:15 PM, Liang, Kan <kan.liang@xxxxxxxxxxxxxxx> wrote:
> > On 3/13/2018 12:00 PM, Andy Shevchenko wrote:
> > > On Tue, Mar 13, 2018 at 5:58 PM, Andy Shevchenko
> > > <andy.shevchenko@xxxxxxxxx> wrote:
> > > > On Tue, Mar 13, 2018 at 3:42 AM, Liang, Kan <kan.liang@xxxxxxxxxxxxxxx>
> > > > wrote:
>
> > > > > +#define SKX_CAPID6             0x9c
>
> > > > > +       pci_read_config_dword(dev, SKX_CAPID6, &val);
>
> > > Moreover, this is too non-flexible. Can't you find a capability based
> > > on CAP ID  + offset?
> >
> > It looks it doesn't use capability.
>
> See below. It would be sad if it's true. (Will need comment in that case)
>
> > 16:1e.3 System peripheral: Intel Corporation Sky Lake-E PCU Registers (rev
> > 04)
> > 00: 86 80 83 20 00 00 00 00 04 00 80 08 00 00 80 00
> > 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
> > 20: 00 00 00 00 00 00 00 00 00 00 00 00 86 80 00 00
> > 30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
>
> Can you instead provide
> % lspci -nk -vvv -xx -s 16:1e.3
> ?

$ lspci -nk -vvv -xx -s 16:1e.3
16:1e.3 0880: 8086:2083 (rev 04)
        Subsystem: 8086:0000
        Control: I/O- Mem- BusMaster- SpecCycle- MemWINV- VGASnoop- 
ParErr- Stepping- SERR- FastB2B- DisINTx-
        Status: Cap- 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- 
<TAbort- <MAbort- >SERR- <PERR- INTx-
00: 86 80 83 20 00 00 00 00 04 00 80 08 00 00 80 00
10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
20: 00 00 00 00 00 00 00 00 00 00 00 00 86 80 00 00
30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00