Re: [PATCH v2 11/13] ARM: dts: ipq8074: Add peripheral nodes

[Sricharan R]

On 3/16/2018 4:17 PM, Abhishek Sahu wrote:
> On 2018-03-16 15:08, Sricharan R wrote:
>> Add serial, i2c, bam, spi, qpic peripheral nodes.
>>
>> Signed-off-by: Sricharan R <sricharan@xxxxxxxxxxxxxx>
>> ---
>> Âarch/arm64/boot/dts/qcom/ipq8074.dtsi | 105 ++++++++++++++++++++++++++++++++++
>> Â1 file changed, 105 insertions(+)
>>
>> diff --git a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
>> b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
>> index 2bc5dec..806fc56 100644
>> --- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
>> +++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
>> @@ -124,6 +124,111 @@
>> ÂÂÂÂÂÂÂÂÂÂÂÂ clock-names = "core", "iface";
>> ÂÂÂÂÂÂÂÂÂÂÂÂ status = "disabled";
>> ÂÂÂÂÂÂÂÂ };
>> +
>> +ÂÂÂÂÂÂÂ blsp_dma: dma@7884000 {
>> +ÂÂÂÂÂÂÂÂÂÂÂ compatible = "qcom,bam-v1.7.0";
>> +ÂÂÂÂÂÂÂÂÂÂÂ reg = <0x07884000 0x2b000>;
> 
> Âwe can remove leading zero. s/0x07884000/0x7884000
> 
>> +ÂÂÂÂÂÂÂÂÂÂÂ interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>;
>> +ÂÂÂÂÂÂÂÂÂÂÂ clocks = <&gcc GCC_BLSP1_AHB_CLK>;
>> +ÂÂÂÂÂÂÂÂÂÂÂ clock-names = "bam_clk";
>> +ÂÂÂÂÂÂÂÂÂÂÂ #dma-cells = <1>;
>> +ÂÂÂÂÂÂÂÂÂÂÂ qcom,ee = <0>;
>> +ÂÂÂÂÂÂÂ };
>> +
>> +ÂÂÂÂÂÂÂ serial_blsp0: serial@78af000 {
>> +ÂÂÂÂÂÂÂÂÂÂÂ compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
>> +ÂÂÂÂÂÂÂÂÂÂÂ reg = <0x78af000 0x200>;
>> +ÂÂÂÂÂÂÂÂÂÂÂ interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
>> +ÂÂÂÂÂÂÂÂÂÂÂ clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>,
>> +ÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂ <&gcc GCC_BLSP1_AHB_CLK>;
>> +ÂÂÂÂÂÂÂÂÂÂÂ clock-names = "core", "iface";
>> +ÂÂÂÂÂÂÂÂÂÂÂ status = "disabled";
>> +ÂÂÂÂÂÂÂ };
>> +
>> +ÂÂÂÂÂÂÂ serial_blsp2: serial@78B1000 {
> 
> ÂFor maintaining uniformity, we can have all address in lower case
> Âs/78B1000/78b1000
> 
>> +ÂÂÂÂÂÂÂÂÂÂÂ compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
>> +ÂÂÂÂÂÂÂÂÂÂÂ reg = <0x78B1000 0x200>;
> 
> Âsame thing, here also
> 
>> +ÂÂÂÂÂÂÂÂÂÂÂ interrupts = <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>;
>> +ÂÂÂÂÂÂÂÂÂÂÂ clocks = <&gcc GCC_BLSP1_UART3_APPS_CLK>,
>> +ÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂ <&gcc GCC_BLSP1_AHB_CLK>;
>> +ÂÂÂÂÂÂÂÂÂÂÂ clock-names = "core", "iface";
>> +ÂÂÂÂÂÂÂÂÂÂÂ dmas = <&blsp_dma 4>,
>> +ÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂ <&blsp_dma 5>;
>> +ÂÂÂÂÂÂÂÂÂÂÂ dma-names = "tx", "rx";
>> +ÂÂÂÂÂÂÂÂÂÂÂ status = "disabled";
>> +ÂÂÂÂÂÂÂ };
>> +
>> +ÂÂÂÂÂÂÂ spi_0: spi@78b5000 {
>> +ÂÂÂÂÂÂÂÂÂÂÂ compatible = "qcom,spi-qup-v2.2.1";
>> +ÂÂÂÂÂÂÂÂÂÂÂ #address-cells = <1>;
>> +ÂÂÂÂÂÂÂÂÂÂÂ #size-cells = <0>;
>> +ÂÂÂÂÂÂÂÂÂÂÂ reg = <0x78b5000 0x600>;
>> +ÂÂÂÂÂÂÂÂÂÂÂ interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
>> +ÂÂÂÂÂÂÂÂÂÂÂ spi-max-frequency = <50000000>;
>> +ÂÂÂÂÂÂÂÂÂÂÂ clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>,
>> +ÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂ <&gcc GCC_BLSP1_AHB_CLK>;
>> +ÂÂÂÂÂÂÂÂÂÂÂ clock-names = "core", "iface";
>> +ÂÂÂÂÂÂÂÂÂÂÂ dmas = <&blsp_dma 12>, <&blsp_dma 13>;
>> +ÂÂÂÂÂÂÂÂÂÂÂ dma-names = "tx", "rx";
>> +ÂÂÂÂÂÂÂÂÂÂÂ status = "disabled";
>> +ÂÂÂÂÂÂÂ };
>> +
>> +ÂÂÂÂÂÂÂ i2c_0: i2c@78b6000 {
>> +ÂÂÂÂÂÂÂÂÂÂÂ compatible = "qcom,i2c-qup-v2.2.1";
>> +ÂÂÂÂÂÂÂÂÂÂÂ #address-cells = <1>;
>> +ÂÂÂÂÂÂÂÂÂÂÂ #size-cells = <0>;
>> +ÂÂÂÂÂÂÂÂÂÂÂ reg = <0x78b6000 0x600>;
>> +ÂÂÂÂÂÂÂÂÂÂÂ interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
>> +ÂÂÂÂÂÂÂÂÂÂÂ clocks = <&gcc GCC_BLSP1_AHB_CLK>,
>> +ÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂ <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>;
>> +ÂÂÂÂÂÂÂÂÂÂÂ clock-names = "iface", "core";
>> + clock-frequency = <400000>;
> 
> Âremove one extra space. clock-frequency = <400000>;
> 
>> +ÂÂÂÂÂÂÂÂÂÂÂ dmas = <&blsp_dma 15>, <&blsp_dma 14>;
>> +ÂÂÂÂÂÂÂÂÂÂÂ dma-names = "rx", "tx";
>> +ÂÂÂÂÂÂÂÂÂÂÂ status = "disabled";
>> +ÂÂÂÂÂÂÂ };
>> +
>> +ÂÂÂÂÂÂÂ i2c_1: i2c@78b7000 {
>> +ÂÂÂÂÂÂÂÂÂÂÂ compatible = "qcom,i2c-qup-v2.2.1";
>> +ÂÂÂÂÂÂÂÂÂÂÂ #address-cells = <1>;
>> +ÂÂÂÂÂÂÂÂÂÂÂ #size-cells = <0>;
>> +ÂÂÂÂÂÂÂÂÂÂÂ reg = <0x78b7000 0x600>;
>> +ÂÂÂÂÂÂÂÂÂÂÂ interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
>> +ÂÂÂÂÂÂÂÂÂÂÂ clocks = <&gcc GCC_BLSP1_AHB_CLK>,
>> +ÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂ <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>;
>> +ÂÂÂÂÂÂÂÂÂÂÂ clock-names = "iface", "core";
>> + clock-frequency = <100000>;
> 
> Âremove one extra space. clock-frequency = <100000>;
> 
> Âwith above changes.
> 
> ÂReviewed-by: Abhishek Sahu <absahu@xxxxxxxxxxxxxx>
> 

 Sure, will take care of all the above. Thanks

Regards,
 Sricharan
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