Re: [PATCH] x86/ioapic: don't use unstable TSC to detect timer IRQ

[Peter Zijlstra]

On Tue, Mar 20, 2018 at 04:42:55PM +0800, Liu, Changcheng wrote:
> In rare case, the TSC is every unstable or can't sync with
> real time hardware clock. 

However did you manage that? Please provide _FAR_ more details.

> diff --git a/arch/x86/include/asm/tsc.h b/arch/x86/include/asm/tsc.h
> index cf5d53c..dcfc5b9 100644
> --- a/arch/x86/include/asm/tsc.h
> +++ b/arch/x86/include/asm/tsc.h
> @@ -17,6 +17,7 @@ typedef unsigned long long cycles_t;
>  
>  extern unsigned int cpu_khz;
>  extern unsigned int tsc_khz;
> +extern int tsc_unstable;
>  
>  extern void disable_TSC(void);
>  
> diff --git a/arch/x86/kernel/apic/io_apic.c b/arch/x86/kernel/apic/io_apic.c
> index 7c55387..0809ec6 100644
> --- a/arch/x86/kernel/apic/io_apic.c
> +++ b/arch/x86/kernel/apic/io_apic.c
> @@ -1643,7 +1643,7 @@ static int __init timer_irq_works(void)
>  	local_save_flags(flags);
>  	local_irq_enable();
>  
> -	if (boot_cpu_has(X86_FEATURE_TSC))
> +	if (boot_cpu_has(X86_FEATURE_TSC) && !tsc_unstable)
>  		delay_with_tsc();
>  	else
>  		delay_without_tsc();
> diff --git a/arch/x86/kernel/tsc.c b/arch/x86/kernel/tsc.c
> index fb43027..27b1bae 100644
> --- a/arch/x86/kernel/tsc.c
> +++ b/arch/x86/kernel/tsc.c
> @@ -36,7 +36,8 @@ EXPORT_SYMBOL(tsc_khz);
>  /*
>   * TSC can be unstable due to cpufreq or due to unsynced TSCs
>   */
> -static int __read_mostly tsc_unstable;
> +int __read_mostly tsc_unstable;
> +EXPORT_SYMBOL(tsc_unstable);
>  
>  /* native_sched_clock() is called before tsc_init(), so
>     we must start with the TSC soft disabled to prevent

No, absolutely not. Even when the TSC is normally deemed unstable, which
typically means it is not sync'ed between cores, it is still perfectly
suitable to be used for delay loops.