Re: [PATCH v1 1/2] phy: Add QMP phy based UFS phy support for sdm845

[Manu Gautam]

Hi Can,


On 3/21/2018 8:12 AM, cang@xxxxxxxxxxxxxx wrote:
> On 2018-03-20 19:30, Can Guo wrote:
>> Add UFS PHY support to make SDM845 UFS work with common PHY framework.
>>
>> Signed-off-by: Can Guo <cang@xxxxxxxxxxxxxx>
>> ---
>> Âdrivers/phy/qualcomm/phy-qcom-qmp.c | 120 +++++++++++++++++++++++++++++++++++-
>> Âdrivers/phy/qualcomm/phy-qcom-qmp.h |ÂÂ 8 +++
>> Â2 files changed, 126 insertions(+), 2 deletions(-)
>>
[snip]
>> +ÂÂÂ /* true, if PCS block has a separate SW_RESET register */
>> +ÂÂÂ bool has_sw_rst;
>> Â};
>>

You should set this for qmp_v3_usb3_uniphy_cfg as well.
Please also mention dependency on my patches [1] and [2] in your cover letter

[1] http://lists-archives.com/linux-kernel/29071659-dt-bindings-phy-qcom-qmp-update-bindings-for-sdm845.html
[2] lists-archives.com/linux-kernel/29071660-phy-qcom-qmp-add-qmp-v3-usb3-uni-phy-support-for-sdm845.html


>> Â/**
>> @@ -636,6 +712,10 @@ static inline void qphy_clrbits(void __iomem
>> *base, u32 offset, u32 val)
>> ÂÂÂÂ "aux", "cfg_ahb", "ref", "com_aux",
>> Â};
>>
>> +static const char * const sdm845_ufs_phy_clk_l[] = {
>> +ÂÂÂ "ref_clk", "ref_aux_clk",
>> +};
>> +
>> Â/* list of resets */
>> Âstatic const char * const msm8996_pciephy_reset_l[] = {
>> ÂÂÂÂ "phy", "common", "cfg",
>> @@ -650,6 +730,10 @@ static inline void qphy_clrbits(void __iomem
>> *base, u32 offset, u32 val)
>> ÂÂÂÂ "vdda-phy", "vdda-pll",
>> Â};
>>
>> +static const char * const sdm845_phy_vreg_l[] = {
>> +ÂÂÂ "vdda-phy", "vdda-pll",
>> +};
>> +
>> Âstatic const struct qmp_phy_cfg msm8996_pciephy_cfg = {
>> ÂÂÂÂ .typeÂÂÂÂÂÂÂÂÂÂÂ = PHY_TYPE_PCIE,
>> ÂÂÂÂ .nlanesÂÂÂÂÂÂÂÂÂÂÂ = 3,
>> @@ -679,6 +763,7 @@ static inline void qphy_clrbits(void __iomem
>> *base, u32 offset, u32 val)
>> ÂÂÂÂ .has_pwrdn_delayÂÂÂ = true,
>> ÂÂÂÂ .pwrdn_delay_minÂÂÂ = POWER_DOWN_DELAY_US_MIN,
>> ÂÂÂÂ .pwrdn_delay_maxÂÂÂ = POWER_DOWN_DELAY_US_MAX,
>> +ÂÂÂ .has_sw_rstÂÂÂÂÂÂÂ = true,
>> Â};
>>
>> Âstatic const struct qmp_phy_cfg msm8996_usb3phy_cfg = {
>> @@ -704,6 +789,7 @@ static inline void qphy_clrbits(void __iomem
>> *base, u32 offset, u32 val)
>> ÂÂÂÂ .start_ctrlÂÂÂÂÂÂÂ = SERDES_START | PCS_START,
>> ÂÂÂÂ .pwrdn_ctrlÂÂÂÂÂÂÂ = SW_PWRDN,
>> ÂÂÂÂ .mask_pcs_readyÂÂÂÂÂÂÂ = PHYSTATUS,
>> +ÂÂÂ .has_sw_rstÂÂÂÂÂÂÂ = true,
>> Â};
>>
>> Â/* list of resets */
>> @@ -740,6 +826,7 @@ static inline void qphy_clrbits(void __iomem
>> *base, u32 offset, u32 val)
>> ÂÂÂÂ .has_pwrdn_delayÂÂÂ = true,
>> ÂÂÂÂ .pwrdn_delay_minÂÂÂ = 995,ÂÂÂÂÂÂÂ /* us */
>> ÂÂÂÂ .pwrdn_delay_maxÂÂÂ = 1005,ÂÂÂÂÂÂÂ /* us */
>> +ÂÂÂ .has_sw_rstÂÂÂÂÂÂÂ = true,
>> Â};
>>
>> Âstatic const struct qmp_phy_cfg qmp_v3_usb3phy_cfg = {
>> @@ -772,6 +859,30 @@ static inline void qphy_clrbits(void __iomem
>> *base, u32 offset, u32 val)
>> ÂÂÂÂ .has_phy_dp_com_ctrlÂÂÂ = true,
>> ÂÂÂÂ .tx_b_lane_offsetÂÂÂ = 0x400,
>> ÂÂÂÂ .rx_b_lane_offsetÂÂÂ = 0x400,
>> +ÂÂÂ .has_sw_rstÂÂÂÂÂÂÂ = true,
>> +};
>> +
>> +static const struct qmp_phy_cfg sdm845_ufsphy_cfg = {
>> +ÂÂÂ .typeÂÂÂÂÂÂÂÂÂÂÂ = PHY_TYPE_UFS,
>> +ÂÂÂ .nlanesÂÂÂÂÂÂÂÂÂÂÂ = 2,
>> +
>> +ÂÂÂ .serdes_tblÂÂÂÂÂÂÂ = sdm845_ufsphy_serdes_tbl,
>> +ÂÂÂ .serdes_tbl_numÂÂÂÂÂÂÂ = ARRAY_SIZE(sdm845_ufsphy_serdes_tbl),
>> +ÂÂÂ .tx_tblÂÂÂÂÂÂÂÂÂÂÂ = sdm845_ufsphy_tx_tbl,
>> +ÂÂÂ .tx_tbl_numÂÂÂÂÂÂÂ = ARRAY_SIZE(sdm845_ufsphy_tx_tbl),
>> +ÂÂÂ .rx_tblÂÂÂÂÂÂÂÂÂÂÂ = sdm845_ufsphy_rx_tbl,
>> +ÂÂÂ .rx_tbl_numÂÂÂÂÂÂÂ = ARRAY_SIZE(sdm845_ufsphy_rx_tbl),
>> +ÂÂÂ .pcs_tblÂÂÂÂÂÂÂ = sdm845_ufsphy_pcs_tbl,
>> +ÂÂÂ .pcs_tbl_numÂÂÂÂÂÂÂ = ARRAY_SIZE(sdm845_ufsphy_pcs_tbl),
>> +ÂÂÂ .clk_listÂÂÂÂÂÂÂ = sdm845_ufs_phy_clk_l,
>> +ÂÂÂ .num_clksÂÂÂÂÂÂÂ = ARRAY_SIZE(sdm845_ufs_phy_clk_l),
>> +ÂÂÂ .vreg_listÂÂÂÂÂÂÂ = sdm845_phy_vreg_l,
>> +ÂÂÂ .num_vregsÂÂÂÂÂÂÂ = ARRAY_SIZE(sdm845_phy_vreg_l),
>> +ÂÂÂ .regsÂÂÂÂÂÂÂÂÂÂÂ = sdm845_ufsphy_regs_layout,
>> +
>> +ÂÂÂ .start_ctrlÂÂÂÂÂÂÂ = SERDES_START,
>> +ÂÂÂ .pwrdn_ctrlÂÂÂÂÂÂÂ = SW_PWRDN,
>> +ÂÂÂ .mask_pcs_readyÂÂÂÂÂÂÂ = PCS_READY,
>> Â};
>>
>> Âstatic void qcom_qmp_phy_configure(void __iomem *base,
>> @@ -998,7 +1109,8 @@ static int qcom_qmp_phy_init(struct phy *phy)
>> ÂÂÂÂÂÂÂÂ usleep_range(cfg->pwrdn_delay_min, cfg->pwrdn_delay_max);
>>
>> ÂÂÂÂ /* Pull PHY out of reset state */
>> -ÂÂÂ qphy_clrbits(pcs, cfg->regs[QPHY_SW_RESET], SW_RESET);
>> +ÂÂÂ if (cfg->has_sw_rst)
>> +ÂÂÂÂÂÂÂ qphy_clrbits(pcs, cfg->regs[QPHY_SW_RESET], SW_RESET);
>> ÂÂÂÂ if (cfg->has_phy_dp_com_ctrl)
>> ÂÂÂÂÂÂÂÂ qphy_clrbits(dp_com, QPHY_V3_DP_COM_SW_RESET, SW_RESET);
>>
>> @@ -1036,7 +1148,8 @@ static int qcom_qmp_phy_exit(struct phy *phy)
>> ÂÂÂÂ clk_disable_unprepare(qphy->pipe_clk);
>>
>> ÂÂÂÂ /* PHY reset */
>> -ÂÂÂ qphy_setbits(qphy->pcs, cfg->regs[QPHY_SW_RESET], SW_RESET);
>> +ÂÂÂ if (cfg->has_sw_rst)
>> +ÂÂÂÂÂÂÂ qphy_setbits(qphy->pcs, cfg->regs[QPHY_SW_RESET], SW_RESET);
>>
>> ÂÂÂÂ /* stop SerDes and Phy-Coding-Sublayer */
>> ÂÂÂÂ qphy_clrbits(qphy->pcs, cfg->regs[QPHY_START_CTRL], cfg->start_ctrl);
>> @@ -1383,6 +1496,9 @@ int qcom_qmp_phy_create(struct device *dev,
>> struct device_node *np, int id)
>> ÂÂÂÂ }, {
>> ÂÂÂÂÂÂÂÂ .compatible = "qcom,qmp-v3-usb3-phy",
>> ÂÂÂÂÂÂÂÂ .data = &qmp_v3_usb3phy_cfg,
>> +ÂÂÂ }, {
>> +ÂÂÂÂÂÂÂ .compatible = "qcom,sdm845-qmp-ufs-phy",
>> +ÂÂÂÂÂÂÂ .data = &sdm845_ufsphy_cfg,
>> ÂÂÂÂ },
>> ÂÂÂÂ { },
>> Â};
>> diff --git a/drivers/phy/qualcomm/phy-qcom-qmp.h
>> b/drivers/phy/qualcomm/phy-qcom-qmp.h
>> index d1c6905..ea4b4dc 100644
>> --- a/drivers/phy/qualcomm/phy-qcom-qmp.h
>> +++ b/drivers/phy/qualcomm/phy-qcom-qmp.h
>> @@ -184,6 +184,8 @@
>> Â#define QSERDES_V3_COM_VCO_TUNE2_MODE0ÂÂÂÂÂÂÂÂÂÂÂ 0x0f8
>> Â#define QSERDES_V3_COM_VCO_TUNE1_MODE1ÂÂÂÂÂÂÂÂÂÂÂ 0x0fc
>> Â#define QSERDES_V3_COM_VCO_TUNE2_MODE1ÂÂÂÂÂÂÂÂÂÂÂ 0x100
>> +#define QSERDES_V3_COM_VCO_TUNE_INITVAL1ÂÂÂÂÂÂÂ 0x104
>> +#define QSERDES_V3_COM_VCO_TUNE_INITVAL2ÂÂÂÂÂÂÂ 0x108
>> Â#define QSERDES_V3_COM_VCO_TUNE_TIMER1ÂÂÂÂÂÂÂÂÂÂÂ 0x11c
>> Â#define QSERDES_V3_COM_VCO_TUNE_TIMER2ÂÂÂÂÂÂÂÂÂÂÂ 0x120
>> Â#define QSERDES_V3_COM_CLK_SELECTÂÂÂÂÂÂÂÂÂÂÂ 0x138
>> @@ -211,8 +213,13 @@
>> Â/* Only for QMP V3 PHY - RX registers */
>> Â#define QSERDES_V3_RX_UCDR_SO_GAIN_HALFÂÂÂÂÂÂÂÂÂÂÂ 0x00c
>> Â#define QSERDES_V3_RX_UCDR_SO_GAINÂÂÂÂÂÂÂÂÂÂÂ 0x014
>> +#define QSERDES_V3_RX_UCDR_SVS_SO_GAIN_HALFÂÂÂÂÂÂÂ 0x024
>> +#define QSERDES_V3_RX_UCDR_SVS_SO_GAIN_QUARTERÂÂÂÂÂÂÂ 0x028
>> +#define QSERDES_V3_RX_UCDR_SVS_SO_GAINÂÂÂÂÂÂÂÂÂÂÂ 0x02c
>> Â#define QSERDES_V3_RX_UCDR_FASTLOCK_FO_GAINÂÂÂÂÂÂÂ 0x030
>> Â#define QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLEÂÂÂ 0x034
>> +#define QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_LOWÂÂÂÂÂÂÂ 0x03c
>> +#define QSERDES_V3_RX_UCDR_PI_CONTROLSÂÂÂÂÂÂÂÂÂÂÂ 0x044
>> Â#define QSERDES_V3_RX_RX_TERM_BWÂÂÂÂÂÂÂÂÂÂÂ 0x07c
>> Â#define QSERDES_V3_RX_RX_EQ_GAIN2_LSBÂÂÂÂÂÂÂÂÂÂÂ 0x0c8
>> Â#define QSERDES_V3_RX_RX_EQ_GAIN2_MSBÂÂÂÂÂÂÂÂÂÂÂ 0x0cc
>> @@ -272,6 +279,7 @@
>> Â#define QPHY_V3_PCS_FLL_CNT_VAL_LÂÂÂÂÂÂÂÂÂÂÂ 0x0cc
>> Â#define QPHY_V3_PCS_FLL_CNT_VAL_H_TOLÂÂÂÂÂÂÂÂÂÂÂ 0x0d0
>> Â#define QPHY_V3_PCS_FLL_MAN_CODEÂÂÂÂÂÂÂÂÂÂÂ 0x0d4
>> +#define QPHY_V3_PCS_MULTI_LANE_CTRL1ÂÂÂÂÂÂÂÂÂÂÂ 0x1c4
>> Â#define QPHY_V3_PCS_RX_SIGDET_LVLÂÂÂÂÂÂÂÂÂÂÂ 0x1d8
>>
>> Â/* Only for QMP V3 PHY - PCS_MISC registers */

-- 
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project