[PATCH v1 - resent 5/5] i2c: busses: Add capability register description to documentation

[michaelsh]

From: Michael Shych <michaelsh@xxxxxxxxxxxx>

It adds capability register description to documentation.

Signed-off-by: Michael Shych <michaelsh@xxxxxxxxxxxx>
---
 Documentation/i2c/busses/i2c-mlxcpld | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/Documentation/i2c/busses/i2c-mlxcpld b/Documentation/i2c/busses/i2c-mlxcpld
index 4e46c44..925904a 100644
--- a/Documentation/i2c/busses/i2c-mlxcpld
+++ b/Documentation/i2c/busses/i2c-mlxcpld
@@ -20,6 +20,10 @@ The next transaction types are supported:
  - Write Byte/Block.
 
 Registers:
+CPBLTY		0x0 - capability reg.
+			Bits [6:5] - transaction length. b01 - 72B is supported,
+			36B in other case.
+			Bit 7 - SMBus block read support.
 CTRL		0x1 - control reg.
 			Resets all the registers.
 HALF_CYC	0x4 - cycle reg.
-- 
2.1.4