On 29/03/18 05:44 AM, Christian KÃnig wrote:
Am 28.03.2018 um 21:53 schrieb Logan Gunthorpe:Yes, but right now we don't have a performant way to check if we are
On 28/03/18 01:44 PM, Christian KÃnig wrote:Well, that an arch hasn't implemented it doesn't mean that we don't have
Well, isn't that exactly what dma_map_resource() is good for? As far asYes, it would be nice, but no arch has implemented this yet. We are just
I can see it makes sure IOMMU is aware of the access route and
translates a CPU address into a PCI Bus address.
I'm using that with the AMD IOMMU driver and at least there it works
perfectly fine.
lucky in the x86 case because that arch is simple and doesn't need to do
anything for P2P (partially due to the Bus and CPU addresses being the
same). But in the general case, you can't rely on it.
the right interface to do it.
doing P2P or not in the dma_map_X() wrappers.
And this is necessary to
check if the DMA ops in use support it or not. We can't have the
dma_map_X() functions do the wrong thing because they don't support it yet.
Devices integrated in the CPU usually only "claim" to be PCIe devices.These are just more reasons why our patchset restricts to devices behind
In reality their memory request path go directly through the integrated
north bridge. The reason for this is simple better throughput/latency.
a switch. And more mess for someone to deal with if they need to relax
that restriction.