On Thu, Mar 29, 2018 at 09:59:03PM +0300, Sergey Suloev wrote:AFAIK in SPI protocol we send and receive at the same time. As soon as the transfer length
There is no need to handle 3/4 empty/full interrupts as the maximumThat assumes that you'll be able to treat the FIFO full interrupt and
supported transfer length in PIO mode is 64 bytes for sun4i-family
SoCs.
drain the FIFO before we have the next byte coming in. This would
require a real time system, and we're not in one of them.
Maxime