On Tue, Apr 3, 2018 at 6:31 AM, Shawn Lin <shawn.lin@xxxxxxxxxxxxxx <mailto:shawn.lin@xxxxxxxxxxxxxx>> wrote:
On 2018/3/30 2:24, oscardagrach wrote:
Need at least one line commit body.
Signed-off-by: oscardagrach <ryan@xxxxxxxxx <mailto:ryan@xxxxxxxxx>>
---
 drivers/mmc/host/dw_mmc-k3.c | 10 ++++++++--
 1 file changed, 8 insertions(+), 2 deletions(-)
diff --git a/drivers/mmc/host/dw_mmc-k3.c
b/drivers/mmc/host/dw_mmc-k3.c
index 89cdb3d533bb..efc546cb4db8 100644
--- a/drivers/mmc/host/dw_mmc-k3.c
+++ b/drivers/mmc/host/dw_mmc-k3.c
@@ -194,8 +194,14 @@ static void dw_mci_hi6220_set_ios(struct
dw_mci *host, struct mmc_ios *ios)
    int ret;
    unsigned int clock;
 -  Âclock = (ios->clock <= 25000000) ? 25000000 : ios->clock;
-
+Â Â Â Â/* CLKDIV must be 1 for DDR52/8-bit mode */
+Â Â Â Âif (ios->bus_width == MMC_BUS_WIDTH_8 &&
+Â Â Â Â Â Â Â Âios->timing == MMC_TIMING_MMC_DDR52) {
+Â Â Â Â Â Â Â Âmci_writel(host, CLKDIV, 0x1);
+Â Â Â Â Â Â Â Âclock = ios->clock;
+Â Â Â Â} else {
+Â Â Â Â Â Â Â Âclock = (ios->clock <= 25000000) ? 25000000 :
ios->clock;
+Â Â Â Â}
I undertand DDR52/8-bit need CLKDIV fixed 1, but shouldn't the following
change is more sensible?
if (ios->bus_width == MMC_BUS_WIDTH_8 && ios->timing ==
MMC_TIMING_MMC_DDR52)
    clock = ios->clock * 2;
else
    clock = (ios->clock <= 25000000) ? 25000000 : ios->clock;
The reason is ios->clock is 52MHz and you could claim 104MHz from the
clock provider and let dw_mmc core take care of the divder to be 1.
Otherwise, you just force it to be DDR52/8-bit with a clk rate of 26MHz.
    ret = clk_set_rate(host->biu_clk, clock);
    if (ret)
        dev_warn(host->dev, "failed to set rate
%uHz\n", clock);
Your feedback is correct. I see the Rockchip dwmmc driver has a similar
implementation. After applying your suggested changes, however, my board
reports "dwmmc_k3 f723d000.dwmmc0: failed to set rate 104000000Hz"
during intialization of eMMC. In addition, I do not see CLKDIV being
set to 1. clk_set_rate fails and I wonder if this is out-of-scope of
the driver.
If I set CLKDIV where I did prior, with your changes, the device fails
to set the clock and falls back to 52 MHz (26 MHz) and works fine, but
again, CLKDIV is reported as 0 (even though it is 1.) One thing of
interest to note is when I manually set the clock by doing:
(echo 104000000 > /sys/kernel/debug/mmc0/clock) the device reports back
'mmc_host mmc0: Bus speed (slot 0) = 198400000Hz (slot req 104000000Hz,
Âactual 99200000HZ div = 1)' which works reliably and clk_set_rate does
not report any error.
I am not sure where to begin debugging these clock issues and welcome
any feedback.