Re: [PATCH v3 3/6] spi: sun6i: restrict transfer length in PIO-mode

[Sergey Suloev]

On 04/06/2018 10:34 AM, Maxime Ripard wrote:
> On Thu, Apr 05, 2018 at 04:44:16PM +0300, Sergey Suloev wrote:
> > On 04/05/2018 04:17 PM, Mark Brown wrote:
> > > On Thu, Apr 05, 2018 at 12:59:35PM +0300, Sergey Suloev wrote:
> > > > On 04/05/2018 12:19 PM, Maxime Ripard wrote:
> > > > > The point of that patch was precisely to allow to send more data than
> > > > > the FIFO. You're breaking that behaviour without any justification,
> > > > > and this is not ok.
> > > > I am sorry, but you can't. That's a hardware limitation.
> > > Are you positive about that?  Normally you can add things to hardware
> > > FIFOs while they're being drained so so long as you can keep data
> > > flowing in at least as fast as it's being consumed.
> > Well, normally yes, but this is not the case with the hardware that I own.
> > My a20 (BPiM1+) and a31 (BPiM2) boards behaves differently. With a transfer
> > larger than FIFO then TC interrupt never happens.
> Because you're not supposed to have a transfer larger than the FIFO,
> but to have to setup at first a transfer the size of the FIFO, and
> then when it's (or starts to be) depleted, fill it up again.

According to what you said the driver must implement 
"transfer_one_message" instead of "transfer_one"

> That's the point of the patch you're reverting, and if it doesn't
> work, you should make it work and not simply revert it.
>
> Maxime