Re: [PATCH v3 3/3] clk: qcom: Add Global Clock controller (GCC) driver for SDM845

[Manu Gautam]

Hi Amit,


On 4/18/2018 6:33 PM, Amit Nischal wrote:
>>> +ÂÂÂÂÂÂ /* Disable the GPLL0 active input to MMSS and GPU via MISC registersÂ*/
>>> +ÂÂÂÂÂÂÂregmap_update_bits(regmap,Â0x09ffc,Â0x3,Â0x3);
>>> +ÂÂÂÂÂÂÂregmap_update_bits(regmap,Â0x71028,Â0x3,Â0x3);
>>
>> IÂthinkÂwe'llÂhaveÂtoÂthrowÂinÂtheÂpipeÂclkÂbranchÂstuffÂinÂhereÂtoo?
>> AndÂthenÂdropÂtheÂpipeÂclksÂfromÂtheÂdriver?
>
> AllÂtheÂUSBÂpipeÂclocksÂwouldÂbeÂtakenÂcare.ÂTheÂPCIEÂpipeÂbranch
> clocksÂwouldÂhaveÂtoÂbeÂexplicitlyÂdisabledÂsoÂasÂtoÂretainÂthe
> memoryÂlogic.ÂOtherwise,ÂitÂwouldÂleadÂtoÂmemoryÂcorruptionÂinÂcase
> the external source is directly disabled without disabling the branch clock. 

PHY driver is same for both USB and PCIE and both PHYs use pipe_clk.
If there is indeed some limitation and pipe_clk cant be left enabled
always then I will suggest to not change pipe_clk handling for USB as well.

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