Re: support for non-uniform SPI NOR flash memories

[Marek Vasut]

On 05/07/2018 07:11 PM, Tudor Ambarus wrote:
> Hi, Marek, all,
> 
> I'm studying Cyrille's patch for non-uniform SPI NOR flash memories:
> https://lkml.org/lkml/2017/4/15/70.
> 
> It's not clear to me whether interleaved regions are possible or not. I
> read the JEDEC Standard No. 216B and it looks like each region is well
> delimited, there is no such thing as interleaved regions (see section
> 6.5):
> 
> "When there is more than one sector size in a device, each contiguous
> group of sectors, that are of the same size, and support the same erase
> types, is called a region."
> 
> If interleaved regions are not possible, the code can be simplified. Do
> I miss something, is there anything else that I should read in this
> regard?
> 
> Apart of how we represent the regions, there is some improvement that we
> can do. When in a region, I see that is preferred the biggest possible
> erase type that meets all the conditions. If so, we can iterate from the
> biggest erase type to the smallest, and when find one that meets all the
> conditions, break the loop.

There are flashes which have larger erase blocks at the beginning/end
and then there are flashes with multiple dies, which support die-wide
erase and chip-wide erase . Not all flashes support everything though.

But indeed there are -- to my knowledge -- no flashes with interleaved
erase blocks. And yes, there could be improvement in erasing exactly the
required chunk of flash with a fitting opcode :)

-- 
Best regards,
Marek Vasut