On Tue, May 08, 2018 at 09:36:24AM +0800, Jeffy Chen wrote:
On 05/08/2018 06:15 AM, Brian Norris wrote:
On the other hand...this also implies there may be a race condition
there, where we might lose an interrupt if there is an edge between the
re-configuration of the polarity in rockchip_irq_demux() and the
clearing/handling of the interrupt (handle_edge_irq() ->
chip->irq_ack()). If we have an edge between there, then we might ack
it, but leave the polarity such that we aren't ready for the next
(inverted) edge.
if let me guess, the unexpected irq we saw is the hardware trying to avoid
losing irq? for example, we set a EDGE_RISING, and the hardware saw the gpio
is already high, then though it might lost an irq, so fake one for safe?
I won't pretend to know what the IC designers were doing, but I don't
think that would resolve the problem I'm talking about. The sequence is
something like:
1. EDGE_BOTH IRQ occurs (e.g., low to high)
2. reconfigure polarity in rockchip_irq_demux() (polarity=low)
3. continue to handle_edge_irq()
4. another HW edge occurs (e.g., high to low)
5. handle_edge_irq() (from 3) acks (clears) IRQ (before a subsequent
rockchip_irq_demux() gets a chance to run and flip the polarity)
...
Now the polarity is still low, but the next trigger should be a
low-to-high edge.
i'll try to confirm it with IC guys.
Brian