Re: [PATCH v2]: perf/x86: store user space frame-pointer value on a sample

From: Alexey Budankov
Date: Mon May 21 2018 - 13:16:57 EST


Hi,

On 21.05.2018 20:23, Andy Lutomirski wrote:
>
>> On May 21, 2018, at 9:51 AM, Alexey Budankov <alexey.budankov@xxxxxxxxxxxxxxx> wrote:
>>
>>
>> Hi Andy,
>>> On 21.05.2018 17:14, Andy Lutomirski wrote:
>>>
>>>> On May 21, 2018, at 5:44 AM, Alexey Budankov <alexey.budankov@xxxxxxxxxxxxxxx> wrote:
>>>>
>>>> Hi Peter,
>>>>
>>>>> On 10.05.2018 13:14, Peter Zijlstra wrote:
>>>>> On Thu, May 10, 2018 at 12:42:38PM +0300, Alexey Budankov wrote:
>>>>>>> The Changelog needs to state that user_regs->bp is in fact valid and
>>>>>>
>>>>>> That actually was tested on binaries compiled without and with BP exposed
>>>>>> and in the latter case proved the value of that change.
>>>>>
>>>>> Mostly works is not the same as 'always initialized', if there are entry
>>>>> paths that do not store that register, then using the value might leak
>>>>> values from the kernel stack, which would be bad.
>>>>>
>>>>> But like said, I think much of the kernel entry code was sanitized with
>>>>> the PTI effort and I suspect things are in fact fine now, but lets wait
>>>>> for Andy to confirm.
>>>>
>>>> It looks like, these days, all registers are saved on system calls, just
>>>> like you anticipated.
>>>>
>>>> So BP register value might be stored into the Perf trace on a sample.
>>>>
>>>> Andy?
>>>
>>> Hmm, I thought I replied. Yes, they are indeed all saved, but Iâm not very excited about committing to doing so forever. But storing BP should be fine.
>>
>> Thanks for explicit confirmation regarding BP register.
>> BTW, do you see any mean to prevent possible unattended regression?
>> I guess it could be some compile time assertion or regression testing.
>
> Write a selftest?

Hmm, that might be. It would be good to have some embedded notification when things change.

>
> The whole perf user regs mechanism is buggy and fragile. I need to massively clean it up at some point.

Yep, making Perf user regs part more robust makes great sense.
It is critical part of perf/core subsystem providing values of IP,SP,BP registers
that are needed for user stack unwinding during Perf trace file post processing.

Thanks,
Alexey

>
>>
>> Thanks,
>> Alexey
>>
>>>
>