Re: [PATCH v2] serial: imx: fix cached UCR2 read on software reset

[Uwe Kleine-König]

On Fri, Apr 20, 2018 at 02:44:07PM +0200, Stefan Agner wrote:
> To reset the UART the SRST needs be cleared (low active). According
> to the documentation the bit will remain active for 4 module clocks
> until it is cleared (set to 1).
> 
> Hence the real register need to be read in case the cached register
> indicates that the SRST bit is zero.
> 
> This bug lead to wrong baudrate because the baud rate register got
> restored before reset completed in imx_flush_buffer.
> 
> Fixes: 3a0ab62f43de ("serial: imx: implement shadow registers for UCRx and UFCR")
> Signed-off-by: Stefan Agner <stefan@xxxxxxxx>
> Reviewed-by: Fabio Estevam <fabio.estevam@xxxxxxx>
> Reviewed-by: Uwe Kleine-König <u.kleine-koenig@xxxxxxxxxxxxxx>

For the record, there is a customer of mine who reports that this commit
breaks rs485 communication on i.MX25 because RTS stops to toggle as
intended.

(Some details: uart3, fsl,uart-has-rtscts, fsl,dte-mode,
linux,rs485-enabled-at-boot-time, native RTS.)

I didn't debug this yet.

Best regards
Uwe

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