On Tue, Jun 12, 2018 at 01:40:30PM +0800, Songjun Wu wrote:Thanks,
From: Hua Ma <hua.ma@xxxxxxxxxxxxxxx>Please split dts files to separate patch.
Add initial support for Intel MIPS interAptiv SoCs made by Intel.
This series will add support for the GRX500 family.
The series allows booting a minimal system using a initramfs.
Signed-off-by: Hua ma <hua.ma@xxxxxxxxxxxxxxx>
Signed-off-by: Songjun Wu <songjun.wu@xxxxxxxxxxxxxxx>
---
arch/mips/Kbuild.platforms | 1 +
arch/mips/Kconfig | 36 ++++
arch/mips/boot/dts/Makefile | 1 +
arch/mips/boot/dts/intel-mips/Makefile | 3 +
arch/mips/boot/dts/intel-mips/easy350_anywan.dts | 20 +++
arch/mips/boot/dts/intel-mips/xrx500.dtsi | 196 +++++++++++++++++++++
The board compatible will be added.diff --git a/arch/mips/boot/dts/intel-mips/easy350_anywan.dts b/arch/mips/boot/dts/intel-mips/easy350_anywan.dtsA board should have a board specific compatible, too.
new file mode 100644
index 000000000000..40177f6cee1e
--- /dev/null
+++ b/arch/mips/boot/dts/intel-mips/easy350_anywan.dts
@@ -0,0 +1,20 @@
+// SPDX-License-Identifier: GPL-2.0
+/dts-v1/;
+
+#include <dt-bindings/interrupt-controller/mips-gic.h>
+#include <dt-bindings/clock/intel,grx500-clk.h>
+
+#include "xrx500.dtsi"
+
+/ {
+ model = "EASY350 ANYWAN (GRX350) Main model";
The memory address will be changed to @20000000.
+ chosen {memory@20000000
+ bootargs = "earlycon=lantiq,0x16600000 clk_ignore_unused";
+ stdout-path = "serial0";
+ };
+
+ memory@0 {
The compatible will be updated in the document.
+ device_type = "memory";This needs to be documented.
+ reg = <0x20000000 0x0e000000>;
+ };
+};
diff --git a/arch/mips/boot/dts/intel-mips/xrx500.dtsi b/arch/mips/boot/dts/intel-mips/xrx500.dtsi
new file mode 100644
index 000000000000..04a068d6d96b
--- /dev/null
+++ b/arch/mips/boot/dts/intel-mips/xrx500.dtsi
@@ -0,0 +1,196 @@
+// SPDX-License-Identifier: GPL-2.0
+
+/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "intel,xrx500";