[RFC PATCH 2/2] mtd: rawnand: marvell: Support page size of 2048 with 8-bit ECC

[Chris Packham]

The MT29F1G08ABAFAWP-ITE:F chip has 2048 byte pages and requires a
minimum ECC strength of 8-bits. Allow for this combination of
requirements using the marvell_nand controller.

Signed-off-by: Chris Packham <chris.packham@xxxxxxxxxxxxxxxxxxx>
---
I've tried to follow the recommended AN-379 from Marvell. They do seem
to have information that covers this particular set of chip requirements
but I'm not confident I've translated their code correctly into the
current marvell_nand implementation.

This is enough to make the nand_scan work but ubi/ubifs fails to initialise
and/or mount so I may have something completely wrong. This may also be
because this chip has internal ECC enabled which cannot be disabled. I
turned up an old thread on this from April last year[1] but I didn't see
anything resulting from this. Can this combination of ECC
implementations even co-exist?

[1] - http://lists.infradead.org/pipermail/linux-mtd/2017-April/073370.html

 drivers/mtd/nand/raw/marvell_nand.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/mtd/nand/raw/marvell_nand.c b/drivers/mtd/nand/raw/marvell_nand.c
index ebb1d141b900..5712df553a8e 100644
--- a/drivers/mtd/nand/raw/marvell_nand.c
+++ b/drivers/mtd/nand/raw/marvell_nand.c
@@ -217,6 +217,7 @@ static const struct marvell_hw_ecc_layout marvell_nfc_layouts[] = {
 	MARVELL_LAYOUT(  512,   512,  1,  1,  1,  512,  8,  8,  0,  0,  0),
 	MARVELL_LAYOUT( 2048,   512,  1,  1,  1, 2048, 40, 24,  0,  0,  0),
 	MARVELL_LAYOUT( 2048,   512,  4,  1,  1, 2048, 32, 30,  0,  0,  0),
+	MARVELL_LAYOUT( 2048,   512,  8,  1,  1, 1024, 0, 30,  1024,  32,  30),
 	MARVELL_LAYOUT( 4096,   512,  4,  2,  2, 2048, 32, 30,  0,  0,  0),
 	MARVELL_LAYOUT( 4096,   512,  8,  5,  4, 1024,  0, 30,  0, 64, 30),
 };
-- 
2.17.1