Re: [PATCH v6 23/29] drm/mediatek: add connection from RDMA2 to DSI2
From: CK Hu
Date: Tue Jun 19 2018 - 04:46:49 EST
On Tue, 2018-06-19 at 15:34 +0800, Stu Hsieh wrote:
> This patch add the connection from RDMA2 to DSI2
>
Reviewed-by: CK Hu <ck.hu@xxxxxxxxxxxx>
> Signed-off-by: Stu Hsieh <stu.hsieh@xxxxxxxxxxxx>
> ---
> drivers/gpu/drm/mediatek/mtk_drm_ddp.c | 8 ++++++++
> 1 file changed, 8 insertions(+)
>
> diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp.c
> index db78fad785e3..e5db1ab51c9b 100644
> --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c
> +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp.c
> @@ -95,6 +95,7 @@
> #define RDMA2_SOUT_DPI0 0x2
> #define RDMA2_SOUT_DPI1 0x3
> #define RDMA2_SOUT_DSI1 0x1
> +#define RDMA2_SOUT_DSI2 0x4
> #define DPI0_SEL_IN_RDMA1 0x1
> #define DPI0_SEL_IN_RDMA2 0x3
> #define DPI1_SEL_IN_RDMA1 (0x1 << 8)
> @@ -102,6 +103,7 @@
> #define DSI1_SEL_IN_RDMA1 0x1
> #define DSI1_SEL_IN_RDMA2 0x4
> #define DSI2_SEL_IN_RDMA1 (0x1 << 16)
> +#define DSI2_SEL_IN_RDMA2 (0x4 << 16)
> #define DSI3_SEL_IN_RDMA1 (0x1 << 16)
> #define COLOR1_SEL_IN_OVL1 0x1
>
> @@ -209,6 +211,9 @@ static unsigned int mtk_ddp_mout_en(enum mtk_ddp_comp_id cur,
> } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI1) {
> *addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT;
> value = RDMA2_SOUT_DSI1;
> + } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI2) {
> + *addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT;
> + value = RDMA2_SOUT_DSI2;
> } else {
> value = 0;
> }
> @@ -249,6 +254,9 @@ static unsigned int mtk_ddp_sel_in(enum mtk_ddp_comp_id cur,
> } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI1) {
> *addr = DISP_REG_CONFIG_DSIE_SEL_IN;
> value = DSI1_SEL_IN_RDMA2;
> + } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI2) {
> + *addr = DISP_REG_CONFIG_DSIE_SEL_IN;
> + value = DSI2_SEL_IN_RDMA2;
> } else if (cur == DDP_COMPONENT_OVL1 && next == DDP_COMPONENT_COLOR1) {
> *addr = DISP_REG_CONFIG_DISP_COLOR1_SEL_IN;
> value = COLOR1_SEL_IN_OVL1;