Re: [PATCH v11 09/13] x86, sgx: basic routines for enclave page cache

From: Jethro Beekman
Date: Tue Jun 19 2018 - 11:44:54 EST


On 2018-06-19 07:08, Jarkko Sakkinen wrote:
On Fri, Jun 08, 2018 at 11:21:48AM -0700, Jethro Beekman wrote:
On 2018-06-08 10:09, Jarkko Sakkinen wrote:
+/*
+ * Writing the LE hash MSRs is extraordinarily expensive, e.g.
+ * 3-4x slower than normal MSRs, so we use a per-cpu cache to
+ * track the last known value of the MSRs to avoid unnecessarily
+ * writing the MSRs with the current value. Because most Linux
+ * kernels will use an LE that is signed with a non-Intel key,

I don't think you can predict what most Linux kernels will be doing. I think
not initializing the cache to the CPU's initial value is fine, but this
particular argument shouldn't appear in the rationale.

Are you just referring to the last sentence or the whole paragraph?

Just the last sentence.

/Jarkko
Jethro

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