Hi David,
Am Mittwoch, 20. Juni 2018, 04:40:35 CEST schrieb David Wu:
å 2018å06æ14æ 16:30, Heiko StÃbner åé:
Am Donnerstag, 14. Juni 2018, 10:14:31 CEST schrieb David Wu:
Hi Heiko,
å 2018å06æ14æ 15:54, Heiko StÃbner åé:
I don't see that new clock documented in the dt-binding.
Also, which clock from the clock-controller does this connect to?
The clock is the "SCLK_GMAC_RMII" at the clock-controller, which could
be set rate by the link speed.
Hmm, while these huge number of clocks are somewhat strange,
shouldn't it be named something with _rmii instead of _speed then?
Okay, it is better to be named _speed.
Also, I don't see any clk_enable action for that new clock, so you could
end up with being off?
The new speed is the parent of the clk_tx_rx, to enable/disable
clk_tx_rx, the new clock would be also enabled/disabled.
Still it is nicer to really enable it, so that the clock-framework can keep
track of usage counts.
Because also no-one hinders the chip-designer from putting a gate in
between in one of the next socs ;-)
Heiko