Re: [PATCH] Fix for clk disable issue on imx6ul

[Fabio Estevam]

Hi Chakra,

On Thu, Jun 21, 2018 at 11:55 PM, Chakra Divi <2chakrass@xxxxxxxxx> wrote:
> isiot engicam board is not booting after the
> commit cf091ee994ec266e33c3a305d6fc8c5ccb1f8acd
> done by <robin@xxxxxxxxxxx>. Modified the
> commit to support imx6ul based SOMs too along
> with imx6ull processors
>
> Signed-off-by: Chakra Divi <chakra@xxxxxxxxxxxx>
> ---
>  drivers/clk/imx/clk-imx6ul.c | 6 ++++--
>  1 file changed, 4 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/clk/imx/clk-imx6ul.c b/drivers/clk/imx/clk-imx6ul.c
> index ba563ba..69ec9f0 100644
> --- a/drivers/clk/imx/clk-imx6ul.c
> +++ b/drivers/clk/imx/clk-imx6ul.c
> @@ -80,7 +80,7 @@ static struct clk *clks[IMX6UL_CLK_END];
>  static struct clk_onecell_data clk_data;
>
>  static int const clks_init_on[] __initconst = {
> -       IMX6UL_CLK_AIPSTZ1, IMX6UL_CLK_AIPSTZ2,
> +       IMX6UL_CLK_AIPSTZ1, IMX6UL_CLK_AIPSTZ2, IMX6UL_CLK_AIPSTZ3,
>         IMX6UL_CLK_AXI, IMX6UL_CLK_ARM, IMX6UL_CLK_ROM,
>         IMX6UL_CLK_MMDC_P0_FAST, IMX6UL_CLK_MMDC_P0_IPG,
>  };
> @@ -358,7 +358,9 @@ static void __init imx6ul_clocks_init(struct device_node *ccm_node)
>         clks[IMX6UL_CLK_GPT2_SERIAL]    = imx_clk_gate2("gpt2_serial",  "perclk",       base + 0x68,    26);
>         clks[IMX6UL_CLK_UART2_IPG]      = imx_clk_gate2("uart2_ipg",    "ipg",          base + 0x68,    28);
>         clks[IMX6UL_CLK_UART2_SERIAL]   = imx_clk_gate2("uart2_serial", "uart_podf",    base + 0x68,    28);
> -       if (clk_on_imx6ull())
> +       if (clk_on_imx6ul())
> +               clks[IMX6UL_CLK_AIPSTZ3]        = imx_clk_gate2("aips_tz3",     "ahb",          base + 0x68,    30);

Looking at the CCM_CCGR0 register (address: 20C_4068) there is no
aips_tz3 clock gate in bits 31-30.

Bits 31-30 are gpio2_clocks and Anson has recently sent a patch adding
support for it:
https://patchwork.kernel.org/patch/10481351/

Please test Anson's patch as it should fix the problem you had.

Regards,

Fabio Estevam