Re: KVM guest sometimes failed to boot because of kernel stack overflow if KPTI is enabled on a hisilicon ARM64 platform.
From: Mark Rutland
Date: Fri Jun 29 2018 - 06:00:05 EST
On Thu, Jun 28, 2018 at 07:24:30PM +0000, Zhangxiquan wrote:
> Do you think this order guarantee (between DC and ldst)is applicable for
> cacheable only , or it is also applicable for device ï
This also applies for device memory.
As I quoted previously, from ARM DDI 0487C.a page D3-2069:
All data cache instructions, other than DC ZVA , that specify an
address:
* Can execute in any order relative to loads or stores that access any
address with the Device memory attribute, or with Normal memory with
Inner Non-cacheable attribute unless a DMB or DSB is executed
between the instructions.
i.e. a DMB is sufficient to provide order between DC and loads/stores
which access device memory.
Thanks,
Mark.