Re: [PATCH 2/2] tools/memory-model: Add write ordering by release-acquire and by locks
From: Will Deacon
Date: Thu Jul 05 2018 - 11:15:19 EST
On Thu, Jul 05, 2018 at 10:57:28AM -0400, Alan Stern wrote:
> On Thu, 5 Jul 2018, Will Deacon wrote:
> > On Thu, Jul 05, 2018 at 10:21:36AM -0400, Alan Stern wrote:
> > > On Wed, 4 Jul 2018, Will Deacon wrote:
> > > > On Tue, Jul 03, 2018 at 01:28:17PM -0400, Alan Stern wrote:
> > > > > Would this be allowed if smp_load_acquire() was implemented with LDAPR?
> > > > > If the answer is yes then we will have to remove the rfi-rel-acq and
> > > > > rel-rf-acq-po relations from the memory model entirely.
> > > >
> > > > I don't understand what you mean by "rfi-rel-acq-po", and I assume you mean
> > > > rel-rfi-acq-po for the other? Sounds like I'm confused here.
> > >
> > > "rfi-rel-acq" is the relation which was removed by the first of my two
> > > patches (it is now back in business since Paul reverted the commits),
> > > and "rel-rf-acq-po" is the relation that was introduced to replace it.
> >
> > Sorry, yes, I realised this after I'd replied. Curious: but why do you name
> > the relations this way around, as opposed to e.g. rel-rfi-acq? It's
> > obviously up to you, but I just couldn't figure out what inspired the
> > ordering.
>
> I no longer remember the reason for naming "rfi-rel-acq" the way I did.
> As you say, it doesn't make a lot of sense.
Fair enough!
> The reason for "rel-rf-acq-po" instead of "rel-rfi-acq-po" was because
> the second of the two patches uses that relation in a context where the
> release and the acquire might very well run on different CPUs.
Ok, that makes sense. I realised that I've only been thinking about RCpc
making a difference in the rfi case, because Armv8 is multi-copy atomic
so we don't allow early forwarding from a release to an RCpc acquire
if they are from different CPUs.
Again, I'd be interested in what other architectures have to say here (i.e.
whether RCpc acquire/release instructions are likely to exist in a non
multi-copy atomic architecture).
Will