Re: [PATCH 2/2] clk: ingenic: Add missing flag for UDC clock
From: Stephen Boyd
Date: Fri Jul 06 2018 - 16:36:02 EST
Quoting Paul Cercueil (2018-06-27 05:14:59)
> The UDC clock of the JZ4740 SoC can be gated, but the data structure
> representing it was missing the CGU_CLK_GATE flag to make it work.
>
> Signed-off-by: Paul Cercueil <paul@xxxxxxxxxxxxxxx>
> ---
Applied to clk-next