Hi
add Rob, I forgotten rob's mail.
On 07/17/2018 11:56 AM, Ludovic Barre wrote:
From: Ludovic Barre <ludovic.barre@xxxxxx>
This patch adds mask parameter to define IRQ mux field.
This field could vary depend of IRQ mux selection register.
To avoid backward compatibility, the drivers set
the legacy value by default.
Signed-off-by: Ludovic Barre <ludovic.barre@xxxxxx>
---
 drivers/pinctrl/stm32/pinctrl-stm32.c | 16 ++++++++++++++--
 1 file changed, 14 insertions(+), 2 deletions(-)
diff --git a/drivers/pinctrl/stm32/pinctrl-stm32.c b/drivers/pinctrl/stm32/pinctrl-stm32.c
index dfed609..f756232 100644
--- a/drivers/pinctrl/stm32/pinctrl-stm32.c
+++ b/drivers/pinctrl/stm32/pinctrl-stm32.c
@@ -46,6 +46,8 @@
 #define STM32_GPIO_PINS_PER_BANK 16
 #define STM32_GPIO_IRQ_LINE 16
+#define SYSCFG_IRQMUX_MASK GENMASK(3, 0)
+
 #define gpio_range_to_bank(chip) \
ÂÂÂÂÂÂÂÂÂ container_of(chip, struct stm32_gpio_bank, range)
@@ -1033,6 +1035,7 @@ static int stm32_pctrl_dt_setup_irq(struct platform_device *pdev,
ÂÂÂÂÂ struct device *dev = &pdev->dev;
ÂÂÂÂÂ struct regmap *rm;
ÂÂÂÂÂ int offset, ret, i;
+ÂÂÂ int mask, mask_width;
ÂÂÂÂÂ parent = of_irq_find_parent(np);
ÂÂÂÂÂ if (!parent)
@@ -1052,12 +1055,21 @@ static int stm32_pctrl_dt_setup_irq(struct platform_device *pdev,
ÂÂÂÂÂ if (ret)
ÂÂÂÂÂÂÂÂÂ return ret;
+ÂÂÂ ret = of_property_read_u32_index(np, "st,syscfg", 2, &mask);
+ÂÂÂ if (ret)
+ÂÂÂÂÂÂÂ mask = SYSCFG_IRQMUX_MASK;
+
+ÂÂÂ mask_width = fls(mask);
+
ÂÂÂÂÂ for (i = 0; i < STM32_GPIO_PINS_PER_BANK; i++) {
ÂÂÂÂÂÂÂÂÂ struct reg_field mux;
ÂÂÂÂÂÂÂÂÂ mux.reg = offset + (i / 4) * 4;
-ÂÂÂÂÂÂÂ mux.lsb = (i % 4) * 4;
-ÂÂÂÂÂÂÂ mux.msb = mux.lsb + 3;
+ÂÂÂÂÂÂÂ mux.lsb = (i % 4) * mask_width;
+ÂÂÂÂÂÂÂ mux.msb = mux.lsb + mask_width - 1;
+
+ÂÂÂÂÂÂÂ dev_dbg(dev, "irqmux%d: reg:%#x, lsb:%d, msb:%d\n",
+ÂÂÂÂÂÂÂÂÂÂÂ i, mux.reg, mux.lsb, mux.msb);
ÂÂÂÂÂÂÂÂÂ pctl->irqmux[i] = devm_regmap_field_alloc(dev, rm, mux);
ÂÂÂÂÂÂÂÂÂ if (IS_ERR(pctl->irqmux[i]))