Re: [PATCH 2/8] clk: tegra: host1x has fractional divider

[Ben Dooks]

On 2018-07-23 12:12, Peter De Schrijver wrote:
> On Mon, Jul 23, 2018 at 10:32:58AM +0100, Ben Dooks wrote:
> > On 2018-07-23 09:50, Peter De Schrijver wrote:
> > >On Fri, Jul 20, 2018 at 02:45:26PM +0100, Ben Dooks wrote:
> > >>The host1x clock according to both tegra2 and tegra3 manuals is
> > >>an 8bit divider with lsb being fractional. This is running into
> > >>an issue where the host1x is being set on a tegra20a system to
> > >>266.4MHz but ends up at 222MHz instead.
> > >>
> > >
> > >The fact the hw has a fractional divider, does not mean we're
> > >allowed to use
> > >it. Due to the non 50% duty cycle of fractional divided clocks,
> > >they are not
> > >allowed for certain peripherals. Do you have information
> > >indicating this is
> > >ok for the host1x clock?
> >
> > Only that's what was setup for the systems we're using.
> > We couldn't match the 2.6 working system without these changes.
>
> On Tegra20 or Tegra30?

I'll check tomorrow when I have access to all the hw involved.

--
Ben