Re: [PATCH 1/2] clk: uniphier: add NAND 200MHz clock

[Stephen Boyd]

Quoting Masahiro Yamada (2018-07-20 01:37:35)
> The Denali NAND controller IP needs three clocks:
> 
>  - clk: controller core clock
> 
>  - clk_x: bus interface clock
> 
>  - ecc_clk: clock at which ECC circuitry is run
> 
> Currently, only the first one (50MHz) is provided.  The rest of the
> two clock ports must be connected to the 200MHz clock line.  Add this.
> 
> Signed-off-by: Masahiro Yamada <yamada.masahiro@xxxxxxxxxxxxx>
> ---

Applied to clk-next