Re: [PATCH v2 4/6] i2c: designware: add MSCC Ocelot support

[Andy Shevchenko]

On Tue, 2018-07-31 at 15:47 +0200, Alexandre Belloni wrote:
> The Microsemi Ocelot I2C controller is a designware IP. It also has a
> second set of registers to allow tweaking SDA hold time and spike
> filtering.
> 

Reviewed-by: Andy Shevchenko <andriy.shevchenko@xxxxxxxxxxxxxxx>

(except the bindings, not my area)

> Cc: Rob Herring <robh+dt@xxxxxxxxxx>
> Signed-off-by: Alexandre Belloni <alexandre.belloni@xxxxxxxxxxx>
> ---
> Changes in v2:
>  - improved binding doc
>  - changed the model handling as suggested by Andy
> 
>  .../bindings/i2c/i2c-designware.txt           |  9 ++++-
>  drivers/i2c/busses/i2c-designware-core.h      |  3 ++
>  drivers/i2c/busses/i2c-designware-platdrv.c   | 40
> +++++++++++++++++++
>  3 files changed, 50 insertions(+), 2 deletions(-)
> 
> diff --git a/Documentation/devicetree/bindings/i2c/i2c-designware.txt
> b/Documentation/devicetree/bindings/i2c/i2c-designware.txt
> index fbb0a6d8b964..0fb17387c735 100644
> --- a/Documentation/devicetree/bindings/i2c/i2c-designware.txt
> +++ b/Documentation/devicetree/bindings/i2c/i2c-designware.txt
> @@ -2,7 +2,8 @@
>  
>  Required properties :
>  
> - - compatible : should be "snps,designware-i2c"
> + - compatible : should be "snps,designware-i2c" or "mscc,ocelot-i2c"
> followed by
> +   "snps,designware-i2c" for fallback
>   - reg : Offset and length of the register set for the device
>   - interrupts : <IRQ> where IRQ is the interrupt number.
>  
> @@ -11,8 +12,12 @@ Recommended properties :
>   - clock-frequency : desired I2C bus clock frequency in Hz.
>  
>  Optional properties :
> + - reg : for "mscc,ocelot-i2c", a second register set to configure
> the SDA hold
> +   time, named ICPU_CFG:TWI_DELAY in the datasheet.
> +
>   - i2c-sda-hold-time-ns : should contain the SDA hold time in
> nanoseconds.
> -   This option is only supported in hardware blocks version 1.11a or
> newer.
> +   This option is only supported in hardware blocks version 1.11a or
> newer and

> +   on Microsemi SoCs ("mscc,ocelot-i2c" compatible).wtf

wtf?

>  
>   - i2c-scl-falling-time-ns : should contain the SCL falling time in
> nanoseconds.
>     This value which is by default 300ns is used to compute the tLOW
> period.
> diff --git a/drivers/i2c/busses/i2c-designware-core.h
> b/drivers/i2c/busses/i2c-designware-core.h
> index 870444bbbcc4..5e240ce9968e 100644
> --- a/drivers/i2c/busses/i2c-designware-core.h
> +++ b/drivers/i2c/busses/i2c-designware-core.h
> @@ -225,6 +225,7 @@
>  struct dw_i2c_dev {
>  	struct device		*dev;
>  	void __iomem		*base;
> +	void __iomem		*ext;
>  	struct completion	cmd_complete;
>  	struct clk		*clk;
>  	struct reset_control	*rst;
> @@ -279,6 +280,8 @@ struct dw_i2c_dev {
>  #define ACCESS_INTR_MASK	0x00000004
>  
>  #define MODEL_CHERRYTRAIL	0x00000100
> +#define MODEL_MSCC_OCELOT	0x00000200
> +#define MODEL_MASK		0x00000f00
>  
>  u32 dw_readl(struct dw_i2c_dev *dev, int offset);
>  void dw_writel(struct dw_i2c_dev *dev, u32 b, int offset);
> diff --git a/drivers/i2c/busses/i2c-designware-platdrv.c
> b/drivers/i2c/busses/i2c-designware-platdrv.c
> index ba142d7c0e05..68619b270b4c 100644
> --- a/drivers/i2c/busses/i2c-designware-platdrv.c
> +++ b/drivers/i2c/busses/i2c-designware-platdrv.c
> @@ -158,11 +158,48 @@ static inline int dw_i2c_acpi_configure(struct
> platform_device *pdev)
>  #endif
>  
>  #ifdef CONFIG_OF
> +#define MSCC_ICPU_CFG_TWI_DELAY		0x0
> +#define MSCC_ICPU_CFG_TWI_DELAY_ENABLE	BIT(0)
> +#define MSCC_ICPU_CFG_TWI_SPIKE_FILTER	0x4
> +
> +static int mscc_twi_set_sda_hold_time(struct dw_i2c_dev *dev)
> +{
> +	writel((dev->sda_hold_time << 1) |
> MSCC_ICPU_CFG_TWI_DELAY_ENABLE,
> +	       dev->ext + MSCC_ICPU_CFG_TWI_DELAY);
> +
> +	return 0;
> +}
> +
> +int dw_i2c_of_configure(struct platform_device *pdev)
> +{
> +	struct dw_i2c_dev *dev = platform_get_drvdata(pdev);
> +	struct resource *mem;
> +
> +	switch (dev->flags & MODEL_MASK) {
> +	case MODEL_MSCC_OCELOT:
> +		mem = platform_get_resource(pdev, IORESOURCE_MEM, 1);
> +		dev->ext = devm_ioremap_resource(&pdev->dev, mem);
> +		if (!IS_ERR(dev->ext))
> +			dev->set_sda_hold_time =
> mscc_twi_set_sda_hold_time;
> +		break;
> +	default:
> +		break;
> +	}
> +
> +	return 0;
> +}
> +
>  static const struct of_device_id dw_i2c_of_match[] = {
>  	{ .compatible = "snps,designware-i2c", },
> +	{ .compatible = "mscc,ocelot-i2c", .data = (void
> *)MODEL_MSCC_OCELOT },
>  	{},
>  };
>  MODULE_DEVICE_TABLE(of, dw_i2c_of_match);
> +#else
> +static inline int dw_i2c_of_configure(struct platform_device *pdev)
> +{
> +	return -ENODEV;
> +}
>  #endif
>  
>  static void i2c_dw_configure_master(struct dw_i2c_dev *dev)
> @@ -275,6 +312,9 @@ static int dw_i2c_plat_probe(struct
> platform_device *pdev)
>  
>  	dev->flags |= (u32)device_get_match_data(&pdev->dev);
>  
> +	if (pdev->dev.of_node)
> +		dw_i2c_of_configure(pdev);
> +
>  	acpi_speed = i2c_acpi_find_bus_speed(&pdev->dev);
>  	/*
>  	 * Some DSTDs use a non standard speed, round down to the
> lowest

-- 
Andy Shevchenko <andriy.shevchenko@xxxxxxxxxxxxxxx>
Intel Finland Oy