Re: [PATCH 09/11] RISC-V: Support per-hart timebase-frequency

From: Atish Patra
Date: Wed Aug 08 2018 - 02:47:18 EST

On 8/6/18 1:34 PM, Palmer Dabbelt wrote:
On Fri, 03 Aug 2018 05:33:57 PDT (-0700), Christoph Hellwig wrote:
On Thu, Aug 02, 2018 at 03:19:49PM -0700, Atish Patra wrote:
On 8/2/18 4:50 AM, Christoph Hellwig wrote:
From: Palmer Dabbelt <palmer@xxxxxxxxxx>

Follow the updated DT specs and read the timebase-frequency from the
CPU 0 node.

However, the DT in the HighFive Unleashed has the entry at the wrong place.

Even the example in github also at wrong place.

DT should be consistent between Documentation and the one in the hardware.
I can fix them in bbl & submit a bbl patch. But I am not sure if that's an
acceptable way to do it.

I'll need to have comments from Palmer and/or someone else at SiFive
here. Personally I really don't care where we document the timebase,
as this patch supports both locations anywhere. For now I'll just update
the commit log to state that more explicitly.

You're welcome to submit a BBL patch to make this all match, but from my
understanding of the device tree spec putting timebase-frequency in either
place should be legal so it's not a critical fix. That said, it's better to
have them match than not match.

ok. I will add it my TODO list as a low priority task. Following DT entries can be fixed for now.

1. timebase-frequency
2. next-level-cache