Re: [PATCH v4 0/2] clk: qcom: Add support for RCG to register for DFS

From: Taniya Das
Date: Tue Aug 21 2018 - 07:36:37 EST

Hello Stephen,

Thanks for the changes, I have tested the changes and would require the change mentioned below for this to work.

On 8/18/2018 11:31 PM, Taniya Das wrote:
Hello Stephen,

I will test these changes and get back.

On 8/18/2018 7:42 AM, Stephen Boyd wrote:
Quoting Taniya Das (2018-08-10 18:53:54)
 [v4]
ÂÂ * Add recalc_clk_ops to calculate the clock frequency reading the current
ÂÂÂÂ perf state, also add CLK_GET_RATE_NOCACHE flag.
ÂÂ * Cleanup 'goto' during mode check in 'clk_rcg2_calculate_freq'.
ÂÂ * cleanup return from function 'com_cc_register_rcg_dfs'.

I want to squash this in. I have only compile tested it. Let me know
what you think.

----8<---
diff --git a/drivers/clk/qcom/clk-rcg.h b/drivers/clk/qcom/clk-rcg.h
index e6300e05d5df..e5eca8a1abe4 100644
--- a/drivers/clk/qcom/clk-rcg.h
+++ b/drivers/clk/qcom/clk-rcg.h
@@ -163,6 +163,15 @@ extern const struct clk_ops clk_pixel_ops;
 extern const struct clk_ops clk_gfx3d_ops;
 extern const struct clk_ops clk_rcg2_shared_ops;
+struct clk_rcg_dfs_data {
+ÂÂÂ struct clk_rcg2 *rcg;
+ÂÂÂ struct clk_init_data *init;
+};
+
+#define DEFINE_RCG_DFS(r) \
+ÂÂÂ { .rcg = &r##_src, .init = &r##_init }
+
 extern int qcom_cc_register_rcg_dfs(struct regmap *regmap,
-ÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂ struct clk_rcg2 **rcgs, int num_clks);
+ÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂ const struct clk_rcg_dfs_data *rcgs,
+ÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂ size_t len);
 #endif
diff --git a/drivers/clk/qcom/clk-rcg2.c b/drivers/clk/qcom/clk-rcg2.c
index 55a5b58cbb15..bbe2a1916296 100644
--- a/drivers/clk/qcom/clk-rcg2.c
+++ b/drivers/clk/qcom/clk-rcg2.c
@@ -1051,48 +1051,24 @@ static unsigned long
 clk_rcg2_dfs_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
 {
ÂÂÂÂÂ struct clk_rcg2 *rcg = to_clk_rcg2(hw);
-ÂÂÂ u32 cfg, hid_div, m = 0, n = 0, mode = 0, mask, level;
-ÂÂÂ int num_parents, i;
-ÂÂÂ unsigned long prate;
-
-ÂÂÂ regmap_read(rcg->clkr.regmap, rcg->cmd_rcgr +
-ÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂ SE_CMD_DFSR_OFFSET, &cfg);
-ÂÂÂ level = (GENMASK(4, 1) & cfg) >> 1;
-
-ÂÂÂ regmap_read(rcg->clkr.regmap, rcg->cmd_rcgr +
-ÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂ SE_PERF_DFSR(level), &cfg);
-ÂÂÂ if (rcg->mnd_width) {
-ÂÂÂÂÂÂÂ mask = BIT(rcg->mnd_width) - 1;
-ÂÂÂÂÂÂÂ regmap_read(rcg->clkr.regmap, rcg->cmd_rcgr +
-ÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂ SE_PERF_M_DFSR(level), &m);
-ÂÂÂÂÂÂÂ m &= mask;
-ÂÂÂÂÂÂÂ regmap_read(rcg->clkr.regmap, rcg->cmd_rcgr +
-ÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂ SE_PERF_N_DFSR(level), &n);
-ÂÂÂÂÂÂÂ n =Â ~n;
-ÂÂÂÂÂÂÂ n &= mask;
-ÂÂÂÂÂÂÂ n += m;
-ÂÂÂÂÂÂÂ mode = cfg & CFG_MODE_MASK;
-ÂÂÂÂÂÂÂ mode >>= CFG_MODE_SHIFT;
-ÂÂÂ }
+ÂÂÂ int ret;
+ÂÂÂ u32 level;
-ÂÂÂ mask = BIT(rcg->hid_width) - 1;
-ÂÂÂ hid_div = cfg >> CFG_SRC_DIV_SHIFT;
-ÂÂÂ hid_div &= mask;
-ÂÂÂ cfg &= CFG_SRC_SEL_MASK;
-ÂÂÂ cfg >>= CFG_SRC_SEL_SHIFT;
+ÂÂÂ regmap_read(rcg->clkr.regmap,
+ÂÂÂÂÂÂÂÂÂÂÂ rcg->cmd_rcgr + SE_CMD_DFSR_OFFSET, &level);
+ÂÂÂ level &= GENMASK(4, 1);
+ÂÂÂ level >>= 1;
-ÂÂÂ num_parents = clk_hw_get_num_parents(hw);
-ÂÂÂ for (i = 0; i < num_parents; i++) {
-ÂÂÂÂÂÂÂ if (cfg == rcg->parent_map[i].cfg) {
-ÂÂÂÂÂÂÂÂÂÂÂ prate = clk_hw_get_rate(
-ÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂ clk_hw_get_parent_by_index(&rcg->clkr.hw, i));
-ÂÂÂÂÂÂÂÂÂÂÂ if (parent_rate != prate)
-ÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂ parent_rate = prate;
+ÂÂÂ if (!rcg->freq_tbl) {
+ÂÂÂÂÂÂÂ ret = clk_rcg2_dfs_populate_freq_table(rcg);

This function would retrieve the parent_rate and if the parent_rate is not ready then it would fail to boot up.

So we have to make sure the parents are registered before these RCGs. That also was one reason for me to not populate the frequency table at recalc.

We would need this patch to make this work.

/* GCC clock registers */
-#define GCC_AGGRE_NOC_PCIE_TBU_CLK 0
-#define GCC_AGGRE_UFS_CARD_AXI_CLK 1
-#define GCC_AGGRE_UFS_PHY_AXI_CLK 2
-#define GCC_AGGRE_USB3_PRIM_AXI_CLK 3
+#define GPLL0 0
+#define GPLL0_OUT_EVEN 1
+#define GPLL0_OUT_MAIN 2
+#define GPLL4 3
#define GCC_AGGRE_USB3_SEC_AXI_CLK 4
#define GCC_BOOT_ROM_AHB_CLK 5
#define GCC_CAMERA_AHB_CLK 6
@@ -172,9 +172,9 @@
#define GCC_VIDEO_AHB_CLK 162
#define GCC_VIDEO_AXI_CLK 163
#define GCC_VIDEO_XO_CLK 164
-#define GPLL0 165
-#define GPLL0_OUT_EVEN 166
-#define GPLL0_OUT_MAIN 167
+#define GCC_AGGRE_NOC_PCIE_TBU_CLK 165
+#define GCC_AGGRE_UFS_CARD_AXI_CLK 166
+#define GCC_AGGRE_UFS_PHY_AXI_CLK 167
#define GCC_GPU_IREF_CLK 168
#define GCC_SDCC1_AHB_CLK 169
#define GCC_SDCC1_APPS_CLK 170
@@ -191,7 +191,7 @@
#define GCC_VS_CTRL_CLK 181
#define GCC_VS_CTRL_CLK_SRC 182
#define GCC_VSENSOR_CLK_SRC 183
-#define GPLL4 184
+#define GCC_AGGRE_USB3_PRIM_AXI_CLK 184


+ÂÂÂÂÂÂÂ if (ret) {
+ÂÂÂÂÂÂÂÂÂÂÂ pr_err("Failed to update DFS tables for %s\n",
+ÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂ clk_hw_get_name(hw));
+ÂÂÂÂÂÂÂÂÂÂÂ return ret;
ÂÂÂÂÂÂÂÂÂ }
ÂÂÂÂÂ }
-
-ÂÂÂ return calc_rate(parent_rate, m, n, mode, hid_div);
+ÂÂÂ return rcg->freq_tbl[level].freq;
 }
 static const struct clk_ops clk_rcg2_dfs_ops = {
@@ -1102,9 +1078,11 @@ static const struct clk_ops clk_rcg2_dfs_ops = {
ÂÂÂÂÂ .recalc_rate = clk_rcg2_dfs_recalc_rate,
 };
-static int clk_rcg2_enable_dfs(struct clk_rcg2 *rcg, struct regmap *regmap)
+static int clk_rcg2_enable_dfs(const struct clk_rcg_dfs_data *data,
+ÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂ struct regmap *regmap)
 {
-ÂÂÂ struct clk_init_data *init;
+ÂÂÂ struct clk_rcg2 *rcg = data->rcg;
+ÂÂÂ struct clk_init_data *init = data->init;
ÂÂÂÂÂ u32 val;
ÂÂÂÂÂ int ret;
@@ -1116,18 +1094,13 @@ static int clk_rcg2_enable_dfs(struct clk_rcg2 *rcg, struct regmap *regmap)
ÂÂÂÂÂ if (!(val & SE_CMD_DFS_EN))
ÂÂÂÂÂÂÂÂÂ return 0;
-ÂÂÂ init = kzalloc(sizeof(*init), GFP_KERNEL);
-ÂÂÂ if (!init)
-ÂÂÂÂÂÂÂ return -ENOMEM;
-
-ÂÂÂ init->name = rcg->clkr.hw.init->name;
-ÂÂÂ init->flags = rcg->clkr.hw.init->flags;
-ÂÂÂ init->parent_names = rcg->clkr.hw.init->parent_names;
-ÂÂÂ init->num_parents = rcg->clkr.hw.init->num_parents;
-ÂÂÂ init->flags = CLK_GET_RATE_NOCACHE;
+ÂÂÂ /*
+ÂÂÂÂ * Rate changes with consumer writing a register in
+ÂÂÂÂ * their own I/O region
+ÂÂÂÂ */
+ÂÂÂ init->flags |= CLK_GET_RATE_NOCACHE;
ÂÂÂÂÂ init->ops = &clk_rcg2_dfs_ops;
-ÂÂÂ rcg->clkr.hw.init = init;
ÂÂÂÂÂ rcg->freq_tbl = NULL;
ÂÂÂÂÂ pr_debug("DFS registered for clk %s\n", init->name);
@@ -1136,14 +1109,14 @@ static int clk_rcg2_enable_dfs(struct clk_rcg2 *rcg, struct regmap *regmap)
 }
 int qcom_cc_register_rcg_dfs(struct regmap *regmap,
-ÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂ struct clk_rcg2 **rcgs, int num_clks)
+ÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂ const struct clk_rcg_dfs_data *rcgs, size_t len)
 {
ÂÂÂÂÂ int i, ret;
-ÂÂÂ for (i = 0; i < num_clks; i++) {
-ÂÂÂÂÂÂÂ ret = clk_rcg2_enable_dfs(rcgs[i], regmap);
+ÂÂÂ for (i = 0; i < len; i++) {
+ÂÂÂÂÂÂÂ ret = clk_rcg2_enable_dfs(&rcgs[i], regmap);
ÂÂÂÂÂÂÂÂÂ if (ret) {
-ÂÂÂÂÂÂÂÂÂÂÂ const char *name = rcgs[i]->clkr.hw.init->name;
+ÂÂÂÂÂÂÂÂÂÂÂ const char *name = rcgs[i].init->name;
ÂÂÂÂÂÂÂÂÂÂÂÂÂ pr_err("DFS register failed for clk %s\n", name);
ÂÂÂÂÂÂÂÂÂÂÂÂÂ return ret;
diff --git a/drivers/clk/qcom/gcc-sdm845.c b/drivers/clk/qcom/gcc-sdm845.c
index fef6732bd7d8..42ab01d33b52 100644
--- a/drivers/clk/qcom/gcc-sdm845.c
+++ b/drivers/clk/qcom/gcc-sdm845.c
@@ -396,18 +396,27 @@ static const struct freq_tbl ftbl_gcc_qupv3_wrap0_s0_clk_src[] = {
ÂÂÂÂÂ { }
 };
+static struct clk_init_data gcc_qupv3_wrap0_s0_clk_init = {
+ÂÂÂ .name = "gcc_qupv3_wrap0_s0_clk_src",
+ÂÂÂ .parent_names = gcc_parent_names_0,
+ÂÂÂ .num_parents = 4,
+ÂÂÂ .ops = &clk_rcg2_shared_ops,
+};
+
 static struct clk_rcg2 gcc_qupv3_wrap0_s0_clk_src = {
ÂÂÂÂÂ .cmd_rcgr = 0x17034,
ÂÂÂÂÂ .mnd_width = 16,
ÂÂÂÂÂ .hid_width = 5,
ÂÂÂÂÂ .parent_map = gcc_parent_map_0,
ÂÂÂÂÂ .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
-ÂÂÂ .clkr.hw.init = &(struct clk_init_data){
-ÂÂÂÂÂÂÂ .name = "gcc_qupv3_wrap0_s0_clk_src",
-ÂÂÂÂÂÂÂ .parent_names = gcc_parent_names_0,
-ÂÂÂÂÂÂÂ .num_parents = 4,
-ÂÂÂÂÂÂÂ .ops = &clk_rcg2_shared_ops,
-ÂÂÂ },
+ÂÂÂ .clkr.hw.init = &gcc_qupv3_wrap0_s0_clk_init,
+};
+
+static struct clk_init_data gcc_qupv3_wrap0_s1_clk_init = {
+ÂÂÂ .name = "gcc_qupv3_wrap0_s1_clk_src",
+ÂÂÂ .parent_names = gcc_parent_names_0,
+ÂÂÂ .num_parents = 4,
+ÂÂÂ .ops = &clk_rcg2_shared_ops,
 };
 static struct clk_rcg2 gcc_qupv3_wrap0_s1_clk_src = {
@@ -416,12 +425,14 @@ static struct clk_rcg2 gcc_qupv3_wrap0_s1_clk_src = {
ÂÂÂÂÂ .hid_width = 5,
ÂÂÂÂÂ .parent_map = gcc_parent_map_0,
ÂÂÂÂÂ .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
-ÂÂÂ .clkr.hw.init = &(struct clk_init_data){
-ÂÂÂÂÂÂÂ .name = "gcc_qupv3_wrap0_s1_clk_src",
-ÂÂÂÂÂÂÂ .parent_names = gcc_parent_names_0,
-ÂÂÂÂÂÂÂ .num_parents = 4,
-ÂÂÂÂÂÂÂ .ops = &clk_rcg2_shared_ops,
-ÂÂÂ },
+ÂÂÂ .clkr.hw.init = &gcc_qupv3_wrap0_s1_clk_init,
+};
+
+static struct clk_init_data gcc_qupv3_wrap0_s2_clk_init = {
+ÂÂÂ .name = "gcc_qupv3_wrap0_s2_clk_src",
+ÂÂÂ .parent_names = gcc_parent_names_0,
+ÂÂÂ .num_parents = 4,
+ÂÂÂ .ops = &clk_rcg2_shared_ops,
 };
 static struct clk_rcg2 gcc_qupv3_wrap0_s2_clk_src = {
@@ -430,12 +441,14 @@ static struct clk_rcg2 gcc_qupv3_wrap0_s2_clk_src = {
ÂÂÂÂÂ .hid_width = 5,
ÂÂÂÂÂ .parent_map = gcc_parent_map_0,
ÂÂÂÂÂ .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
-ÂÂÂ .clkr.hw.init = &(struct clk_init_data){
-ÂÂÂÂÂÂÂ .name = "gcc_qupv3_wrap0_s2_clk_src",
-ÂÂÂÂÂÂÂ .parent_names = gcc_parent_names_0,
-ÂÂÂÂÂÂÂ .num_parents = 4,
-ÂÂÂÂÂÂÂ .ops = &clk_rcg2_shared_ops,
-ÂÂÂ },
+ÂÂÂ .clkr.hw.init = &gcc_qupv3_wrap0_s2_clk_init,
+};
+
+static struct clk_init_data gcc_qupv3_wrap0_s3_clk_init = {
+ÂÂÂ .name = "gcc_qupv3_wrap0_s3_clk_src",
+ÂÂÂ .parent_names = gcc_parent_names_0,
+ÂÂÂ .num_parents = 4,
+ÂÂÂ .ops = &clk_rcg2_shared_ops,
 };
 static struct clk_rcg2 gcc_qupv3_wrap0_s3_clk_src = {
@@ -444,12 +457,14 @@ static struct clk_rcg2 gcc_qupv3_wrap0_s3_clk_src = {
ÂÂÂÂÂ .hid_width = 5,
ÂÂÂÂÂ .parent_map = gcc_parent_map_0,
ÂÂÂÂÂ .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
-ÂÂÂ .clkr.hw.init = &(struct clk_init_data){
-ÂÂÂÂÂÂÂ .name = "gcc_qupv3_wrap0_s3_clk_src",
-ÂÂÂÂÂÂÂ .parent_names = gcc_parent_names_0,
-ÂÂÂÂÂÂÂ .num_parents = 4,
-ÂÂÂÂÂÂÂ .ops = &clk_rcg2_shared_ops,
-ÂÂÂ },
+ÂÂÂ .clkr.hw.init = &gcc_qupv3_wrap0_s3_clk_init,
+};
+
+static struct clk_init_data gcc_qupv3_wrap0_s4_clk_init = {
+ÂÂÂ .name = "gcc_qupv3_wrap0_s4_clk_src",
+ÂÂÂ .parent_names = gcc_parent_names_0,
+ÂÂÂ .num_parents = 4,
+ÂÂÂ .ops = &clk_rcg2_shared_ops,
 };
 static struct clk_rcg2 gcc_qupv3_wrap0_s4_clk_src = {
@@ -458,12 +473,14 @@ static struct clk_rcg2 gcc_qupv3_wrap0_s4_clk_src = {
ÂÂÂÂÂ .hid_width = 5,
ÂÂÂÂÂ .parent_map = gcc_parent_map_0,
ÂÂÂÂÂ .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
-ÂÂÂ .clkr.hw.init = &(struct clk_init_data){
-ÂÂÂÂÂÂÂ .name = "gcc_qupv3_wrap0_s4_clk_src",
-ÂÂÂÂÂÂÂ .parent_names = gcc_parent_names_0,
-ÂÂÂÂÂÂÂ .num_parents = 4,
-ÂÂÂÂÂÂÂ .ops = &clk_rcg2_shared_ops,
-ÂÂÂ },
+ÂÂÂ .clkr.hw.init = &gcc_qupv3_wrap0_s4_clk_init,
+};
+
+static struct clk_init_data gcc_qupv3_wrap0_s5_clk_init = {
+ÂÂÂ .name = "gcc_qupv3_wrap0_s5_clk_src",
+ÂÂÂ .parent_names = gcc_parent_names_0,
+ÂÂÂ .num_parents = 4,
+ÂÂÂ .ops = &clk_rcg2_shared_ops,
 };
 static struct clk_rcg2 gcc_qupv3_wrap0_s5_clk_src = {
@@ -472,12 +489,14 @@ static struct clk_rcg2 gcc_qupv3_wrap0_s5_clk_src = {
ÂÂÂÂÂ .hid_width = 5,
ÂÂÂÂÂ .parent_map = gcc_parent_map_0,
ÂÂÂÂÂ .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
-ÂÂÂ .clkr.hw.init = &(struct clk_init_data){
-ÂÂÂÂÂÂÂ .name = "gcc_qupv3_wrap0_s5_clk_src",
-ÂÂÂÂÂÂÂ .parent_names = gcc_parent_names_0,
-ÂÂÂÂÂÂÂ .num_parents = 4,
-ÂÂÂÂÂÂÂ .ops = &clk_rcg2_shared_ops,
-ÂÂÂ },
+ÂÂÂ .clkr.hw.init = &gcc_qupv3_wrap0_s5_clk_init,
+};
+
+static struct clk_init_data gcc_qupv3_wrap0_s6_clk_init = {
+ÂÂÂ .name = "gcc_qupv3_wrap0_s6_clk_src",
+ÂÂÂ .parent_names = gcc_parent_names_0,
+ÂÂÂ .num_parents = 4,
+ÂÂÂ .ops = &clk_rcg2_shared_ops,
 };
 static struct clk_rcg2 gcc_qupv3_wrap0_s6_clk_src = {
@@ -486,12 +505,14 @@ static struct clk_rcg2 gcc_qupv3_wrap0_s6_clk_src = {
ÂÂÂÂÂ .hid_width = 5,
ÂÂÂÂÂ .parent_map = gcc_parent_map_0,
ÂÂÂÂÂ .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
-ÂÂÂ .clkr.hw.init = &(struct clk_init_data){
-ÂÂÂÂÂÂÂ .name = "gcc_qupv3_wrap0_s6_clk_src",
-ÂÂÂÂÂÂÂ .parent_names = gcc_parent_names_0,
-ÂÂÂÂÂÂÂ .num_parents = 4,
-ÂÂÂÂÂÂÂ .ops = &clk_rcg2_shared_ops,
-ÂÂÂ },
+ÂÂÂ .clkr.hw.init = &gcc_qupv3_wrap0_s6_clk_init,
+};
+
+static struct clk_init_data gcc_qupv3_wrap0_s7_clk_init = {
+ÂÂÂ .name = "gcc_qupv3_wrap0_s7_clk_src",
+ÂÂÂ .parent_names = gcc_parent_names_0,
+ÂÂÂ .num_parents = 4,
+ÂÂÂ .ops = &clk_rcg2_shared_ops,
 };
 static struct clk_rcg2 gcc_qupv3_wrap0_s7_clk_src = {
@@ -500,12 +521,14 @@ static struct clk_rcg2 gcc_qupv3_wrap0_s7_clk_src = {
ÂÂÂÂÂ .hid_width = 5,
ÂÂÂÂÂ .parent_map = gcc_parent_map_0,
ÂÂÂÂÂ .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
-ÂÂÂ .clkr.hw.init = &(struct clk_init_data){
-ÂÂÂÂÂÂÂ .name = "gcc_qupv3_wrap0_s7_clk_src",
-ÂÂÂÂÂÂÂ .parent_names = gcc_parent_names_0,
-ÂÂÂÂÂÂÂ .num_parents = 4,
-ÂÂÂÂÂÂÂ .ops = &clk_rcg2_shared_ops,
-ÂÂÂ },
+ÂÂÂ .clkr.hw.init = &gcc_qupv3_wrap0_s7_clk_init,
+};
+
+static struct clk_init_data gcc_qupv3_wrap1_s0_clk_init = {
+ÂÂÂ .name = "gcc_qupv3_wrap1_s0_clk_src",
+ÂÂÂ .parent_names = gcc_parent_names_0,
+ÂÂÂ .num_parents = 4,
+ÂÂÂ .ops = &clk_rcg2_shared_ops,
 };
 static struct clk_rcg2 gcc_qupv3_wrap1_s0_clk_src = {
@@ -514,12 +537,14 @@ static struct clk_rcg2 gcc_qupv3_wrap1_s0_clk_src = {
ÂÂÂÂÂ .hid_width = 5,
ÂÂÂÂÂ .parent_map = gcc_parent_map_0,
ÂÂÂÂÂ .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
-ÂÂÂ .clkr.hw.init = &(struct clk_init_data){
-ÂÂÂÂÂÂÂ .name = "gcc_qupv3_wrap1_s0_clk_src",
-ÂÂÂÂÂÂÂ .parent_names = gcc_parent_names_0,
-ÂÂÂÂÂÂÂ .num_parents = 4,
-ÂÂÂÂÂÂÂ .ops = &clk_rcg2_shared_ops,
-ÂÂÂ },
+ÂÂÂ .clkr.hw.init = &gcc_qupv3_wrap1_s0_clk_init,
+};
+
+static struct clk_init_data gcc_qupv3_wrap1_s1_clk_init = {
+ÂÂÂ .name = "gcc_qupv3_wrap1_s1_clk_src",
+ÂÂÂ .parent_names = gcc_parent_names_0,
+ÂÂÂ .num_parents = 4,
+ÂÂÂ .ops = &clk_rcg2_shared_ops,
 };
 static struct clk_rcg2 gcc_qupv3_wrap1_s1_clk_src = {
@@ -528,12 +553,14 @@ static struct clk_rcg2 gcc_qupv3_wrap1_s1_clk_src = {
ÂÂÂÂÂ .hid_width = 5,
ÂÂÂÂÂ .parent_map = gcc_parent_map_0,
ÂÂÂÂÂ .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
-ÂÂÂ .clkr.hw.init = &(struct clk_init_data){
-ÂÂÂÂÂÂÂ .name = "gcc_qupv3_wrap1_s1_clk_src",
-ÂÂÂÂÂÂÂ .parent_names = gcc_parent_names_0,
-ÂÂÂÂÂÂÂ .num_parents = 4,
-ÂÂÂÂÂÂÂ .ops = &clk_rcg2_shared_ops,
-ÂÂÂ },
+ÂÂÂ .clkr.hw.init = &gcc_qupv3_wrap1_s1_clk_init,
+};
+
+static struct clk_init_data gcc_qupv3_wrap1_s2_clk_init = {
+ÂÂÂ .name = "gcc_qupv3_wrap1_s2_clk_src",
+ÂÂÂ .parent_names = gcc_parent_names_0,
+ÂÂÂ .num_parents = 4,
+ÂÂÂ .ops = &clk_rcg2_shared_ops,
 };
 static struct clk_rcg2 gcc_qupv3_wrap1_s2_clk_src = {
@@ -542,12 +569,14 @@ static struct clk_rcg2 gcc_qupv3_wrap1_s2_clk_src = {
ÂÂÂÂÂ .hid_width = 5,
ÂÂÂÂÂ .parent_map = gcc_parent_map_0,
ÂÂÂÂÂ .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
-ÂÂÂ .clkr.hw.init = &(struct clk_init_data){
-ÂÂÂÂÂÂÂ .name = "gcc_qupv3_wrap1_s2_clk_src",
-ÂÂÂÂÂÂÂ .parent_names = gcc_parent_names_0,
-ÂÂÂÂÂÂÂ .num_parents = 4,
-ÂÂÂÂÂÂÂ .ops = &clk_rcg2_shared_ops,
-ÂÂÂ },
+ÂÂÂ .clkr.hw.init = &gcc_qupv3_wrap1_s2_clk_init,
+};
+
+static struct clk_init_data gcc_qupv3_wrap1_s3_clk_init = {
+ÂÂÂ .name = "gcc_qupv3_wrap1_s3_clk_src",
+ÂÂÂ .parent_names = gcc_parent_names_0,
+ÂÂÂ .num_parents = 4,
+ÂÂÂ .ops = &clk_rcg2_shared_ops,
 };
 static struct clk_rcg2 gcc_qupv3_wrap1_s3_clk_src = {
@@ -556,12 +585,14 @@ static struct clk_rcg2 gcc_qupv3_wrap1_s3_clk_src = {
ÂÂÂÂÂ .hid_width = 5,
ÂÂÂÂÂ .parent_map = gcc_parent_map_0,
ÂÂÂÂÂ .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
-ÂÂÂ .clkr.hw.init = &(struct clk_init_data){
-ÂÂÂÂÂÂÂ .name = "gcc_qupv3_wrap1_s3_clk_src",
-ÂÂÂÂÂÂÂ .parent_names = gcc_parent_names_0,
-ÂÂÂÂÂÂÂ .num_parents = 4,
-ÂÂÂÂÂÂÂ .ops = &clk_rcg2_shared_ops,
-ÂÂÂ },
+ÂÂÂ .clkr.hw.init = &gcc_qupv3_wrap1_s3_clk_init,
+};
+
+static struct clk_init_data gcc_qupv3_wrap1_s4_clk_init = {
+ÂÂÂ .name = "gcc_qupv3_wrap1_s4_clk_src",
+ÂÂÂ .parent_names = gcc_parent_names_0,
+ÂÂÂ .num_parents = 4,
+ÂÂÂ .ops = &clk_rcg2_shared_ops,
 };
 static struct clk_rcg2 gcc_qupv3_wrap1_s4_clk_src = {
@@ -570,12 +601,14 @@ static struct clk_rcg2 gcc_qupv3_wrap1_s4_clk_src = {
ÂÂÂÂÂ .hid_width = 5,
ÂÂÂÂÂ .parent_map = gcc_parent_map_0,
ÂÂÂÂÂ .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
-ÂÂÂ .clkr.hw.init = &(struct clk_init_data){
-ÂÂÂÂÂÂÂ .name = "gcc_qupv3_wrap1_s4_clk_src",
-ÂÂÂÂÂÂÂ .parent_names = gcc_parent_names_0,
-ÂÂÂÂÂÂÂ .num_parents = 4,
-ÂÂÂÂÂÂÂ .ops = &clk_rcg2_shared_ops,
-ÂÂÂ },
+ÂÂÂ .clkr.hw.init = &gcc_qupv3_wrap1_s4_clk_init,
+};
+
+static struct clk_init_data gcc_qupv3_wrap1_s5_clk_init = {
+ÂÂÂ .name = "gcc_qupv3_wrap1_s5_clk_src",
+ÂÂÂ .parent_names = gcc_parent_names_0,
+ÂÂÂ .num_parents = 4,
+ÂÂÂ .ops = &clk_rcg2_shared_ops,
 };
 static struct clk_rcg2 gcc_qupv3_wrap1_s5_clk_src = {
@@ -584,12 +617,14 @@ static struct clk_rcg2 gcc_qupv3_wrap1_s5_clk_src = {
ÂÂÂÂÂ .hid_width = 5,
ÂÂÂÂÂ .parent_map = gcc_parent_map_0,
ÂÂÂÂÂ .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
-ÂÂÂ .clkr.hw.init = &(struct clk_init_data){
-ÂÂÂÂÂÂÂ .name = "gcc_qupv3_wrap1_s5_clk_src",
-ÂÂÂÂÂÂÂ .parent_names = gcc_parent_names_0,
-ÂÂÂÂÂÂÂ .num_parents = 4,
-ÂÂÂÂÂÂÂ .ops = &clk_rcg2_shared_ops,
-ÂÂÂ },
+ÂÂÂ .clkr.hw.init = &gcc_qupv3_wrap1_s5_clk_init,
+};
+
+static struct clk_init_data gcc_qupv3_wrap1_s6_clk_init = {
+ÂÂÂ .name = "gcc_qupv3_wrap1_s6_clk_src",
+ÂÂÂ .parent_names = gcc_parent_names_0,
+ÂÂÂ .num_parents = 4,
+ÂÂÂ .ops = &clk_rcg2_shared_ops,
 };
 static struct clk_rcg2 gcc_qupv3_wrap1_s6_clk_src = {
@@ -598,12 +633,14 @@ static struct clk_rcg2 gcc_qupv3_wrap1_s6_clk_src = {
ÂÂÂÂÂ .hid_width = 5,
ÂÂÂÂÂ .parent_map = gcc_parent_map_0,
ÂÂÂÂÂ .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
-ÂÂÂ .clkr.hw.init = &(struct clk_init_data){
-ÂÂÂÂÂÂÂ .name = "gcc_qupv3_wrap1_s6_clk_src",
-ÂÂÂÂÂÂÂ .parent_names = gcc_parent_names_0,
-ÂÂÂÂÂÂÂ .num_parents = 4,
-ÂÂÂÂÂÂÂ .ops = &clk_rcg2_shared_ops,
-ÂÂÂ },
+ÂÂÂ .clkr.hw.init = &gcc_qupv3_wrap1_s6_clk_init,
+};
+
+static struct clk_init_data gcc_qupv3_wrap1_s7_clk_init = {
+ÂÂÂ .name = "gcc_qupv3_wrap1_s7_clk_src",
+ÂÂÂ .parent_names = gcc_parent_names_0,
+ÂÂÂ .num_parents = 4,
+ÂÂÂ .ops = &clk_rcg2_shared_ops,
 };
 static struct clk_rcg2 gcc_qupv3_wrap1_s7_clk_src = {
@@ -612,12 +649,7 @@ static struct clk_rcg2 gcc_qupv3_wrap1_s7_clk_src = {
ÂÂÂÂÂ .hid_width = 5,
ÂÂÂÂÂ .parent_map = gcc_parent_map_0,
ÂÂÂÂÂ .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
-ÂÂÂ .clkr.hw.init = &(struct clk_init_data){
-ÂÂÂÂÂÂÂ .name = "gcc_qupv3_wrap1_s7_clk_src",
-ÂÂÂÂÂÂÂ .parent_names = gcc_parent_names_0,
-ÂÂÂÂÂÂÂ .num_parents = 4,
-ÂÂÂÂÂÂÂ .ops = &clk_rcg2_shared_ops,
-ÂÂÂ },
+ÂÂÂ .clkr.hw.init = &gcc_qupv3_wrap1_s7_clk_init,
 };
 static const struct freq_tbl ftbl_gcc_sdcc2_apps_clk_src[] = {
@@ -3458,23 +3490,23 @@ static const struct of_device_id gcc_sdm845_match_table[] = {
 };
 MODULE_DEVICE_TABLE(of, gcc_sdm845_match_table);
-static struct clk_rcg2 *gcc_dfs_clocks[] = {
-ÂÂÂ &gcc_qupv3_wrap0_s0_clk_src,
-ÂÂÂ &gcc_qupv3_wrap0_s1_clk_src,
-ÂÂÂ &gcc_qupv3_wrap0_s2_clk_src,
-ÂÂÂ &gcc_qupv3_wrap0_s3_clk_src,
-ÂÂÂ &gcc_qupv3_wrap0_s4_clk_src,
-ÂÂÂ &gcc_qupv3_wrap0_s5_clk_src,
-ÂÂÂ &gcc_qupv3_wrap0_s6_clk_src,
-ÂÂÂ &gcc_qupv3_wrap0_s7_clk_src,
-ÂÂÂ &gcc_qupv3_wrap1_s0_clk_src,
-ÂÂÂ &gcc_qupv3_wrap1_s1_clk_src,
-ÂÂÂ &gcc_qupv3_wrap1_s2_clk_src,
-ÂÂÂ &gcc_qupv3_wrap1_s3_clk_src,
-ÂÂÂ &gcc_qupv3_wrap1_s4_clk_src,
-ÂÂÂ &gcc_qupv3_wrap1_s5_clk_src,
-ÂÂÂ &gcc_qupv3_wrap1_s6_clk_src,
-ÂÂÂ &gcc_qupv3_wrap1_s7_clk_src,
+static const struct clk_rcg_dfs_data gcc_dfs_clocks[] = {
+ÂÂÂ DEFINE_RCG_DFS(gcc_qupv3_wrap0_s0_clk),
+ÂÂÂ DEFINE_RCG_DFS(gcc_qupv3_wrap0_s1_clk),
+ÂÂÂ DEFINE_RCG_DFS(gcc_qupv3_wrap0_s2_clk),
+ÂÂÂ DEFINE_RCG_DFS(gcc_qupv3_wrap0_s3_clk),
+ÂÂÂ DEFINE_RCG_DFS(gcc_qupv3_wrap0_s4_clk),
+ÂÂÂ DEFINE_RCG_DFS(gcc_qupv3_wrap0_s5_clk),
+ÂÂÂ DEFINE_RCG_DFS(gcc_qupv3_wrap0_s6_clk),
+ÂÂÂ DEFINE_RCG_DFS(gcc_qupv3_wrap0_s7_clk),
+ÂÂÂ DEFINE_RCG_DFS(gcc_qupv3_wrap1_s0_clk),
+ÂÂÂ DEFINE_RCG_DFS(gcc_qupv3_wrap1_s1_clk),
+ÂÂÂ DEFINE_RCG_DFS(gcc_qupv3_wrap1_s2_clk),
+ÂÂÂ DEFINE_RCG_DFS(gcc_qupv3_wrap1_s3_clk),
+ÂÂÂ DEFINE_RCG_DFS(gcc_qupv3_wrap1_s4_clk),
+ÂÂÂ DEFINE_RCG_DFS(gcc_qupv3_wrap1_s5_clk),
+ÂÂÂ DEFINE_RCG_DFS(gcc_qupv3_wrap1_s6_clk),
+ÂÂÂ DEFINE_RCG_DFS(gcc_qupv3_wrap1_s7_clk),
 };
 static int gcc_sdm845_probe(struct platform_device *pdev)



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