Re: [PATCH 1/3] clk: ingenic: Add proper Kconfig entries

[kbuild test robot]

Hi Paul,

Thank you for the patch! Perhaps something to improve:

[auto build test WARNING on clk/clk-next]
[also build test WARNING on v4.18 next-20180821]
[if your patch is applied to the wrong git tree, please drop us a note to help improve the system]

url:    https://github.com/0day-ci/linux/commits/Paul-Cercueil/clk-ingenic-Add-proper-Kconfig-entries/20180822-003241
base:   https://git.kernel.org/pub/scm/linux/kernel/git/clk/linux.git clk-next
reproduce:
        # apt-get install sparse
        make ARCH=x86_64 allmodconfig
        make C=1 CF=-D__CHECK_ENDIAN__


sparse warnings: (new ones prefixed by >>)

>> drivers/clk/ingenic/cgu.c:137:13: sparse: expression using sizeof(void)
>> drivers/clk/ingenic/cgu.c:137:13: sparse: expression using sizeof(void)
   drivers/clk/ingenic/cgu.c:138:13: sparse: expression using sizeof(void)
   drivers/clk/ingenic/cgu.c:138:13: sparse: expression using sizeof(void)
   drivers/clk/ingenic/cgu.c:141:13: sparse: expression using sizeof(void)
   drivers/clk/ingenic/cgu.c:141:13: sparse: expression using sizeof(void)
   drivers/clk/ingenic/cgu.c:142:13: sparse: expression using sizeof(void)
   drivers/clk/ingenic/cgu.c:142:13: sparse: expression using sizeof(void)
   drivers/clk/ingenic/cgu.c:408:15: sparse: expression using sizeof(void)
   drivers/clk/ingenic/cgu.c:408:15: sparse: expression using sizeof(void)
   drivers/clk/ingenic/cgu.c:409:15: sparse: expression using sizeof(void)
   include/linux/slab.h:631:13: sparse: undefined identifier '__builtin_mul_overflow'

vim +137 drivers/clk/ingenic/cgu.c

b066303f Paul Burton 2015-05-24  120  
b066303f Paul Burton 2015-05-24  121  static unsigned long
b066303f Paul Burton 2015-05-24  122  ingenic_pll_calc(const struct ingenic_cgu_clk_info *clk_info,
b066303f Paul Burton 2015-05-24  123  		 unsigned long rate, unsigned long parent_rate,
b066303f Paul Burton 2015-05-24  124  		 unsigned *pm, unsigned *pn, unsigned *pod)
b066303f Paul Burton 2015-05-24  125  {
b066303f Paul Burton 2015-05-24  126  	const struct ingenic_cgu_pll_info *pll_info;
b066303f Paul Burton 2015-05-24  127  	unsigned m, n, od;
b066303f Paul Burton 2015-05-24  128  
b066303f Paul Burton 2015-05-24  129  	pll_info = &clk_info->pll;
b066303f Paul Burton 2015-05-24  130  	od = 1;
b066303f Paul Burton 2015-05-24  131  
b066303f Paul Burton 2015-05-24  132  	/*
b066303f Paul Burton 2015-05-24  133  	 * The frequency after the input divider must be between 10 and 50 MHz.
b066303f Paul Burton 2015-05-24  134  	 * The highest divider yields the best resolution.
b066303f Paul Burton 2015-05-24  135  	 */
b066303f Paul Burton 2015-05-24  136  	n = parent_rate / (10 * MHZ);
b066303f Paul Burton 2015-05-24 @137  	n = min_t(unsigned, n, 1 << clk_info->pll.n_bits);
b066303f Paul Burton 2015-05-24  138  	n = max_t(unsigned, n, pll_info->n_offset);
b066303f Paul Burton 2015-05-24  139  
b066303f Paul Burton 2015-05-24  140  	m = (rate / MHZ) * od * n / (parent_rate / MHZ);
b066303f Paul Burton 2015-05-24  141  	m = min_t(unsigned, m, 1 << clk_info->pll.m_bits);
b066303f Paul Burton 2015-05-24  142  	m = max_t(unsigned, m, pll_info->m_offset);
b066303f Paul Burton 2015-05-24  143  
b066303f Paul Burton 2015-05-24  144  	if (pm)
b066303f Paul Burton 2015-05-24  145  		*pm = m;
b066303f Paul Burton 2015-05-24  146  	if (pn)
b066303f Paul Burton 2015-05-24  147  		*pn = n;
b066303f Paul Burton 2015-05-24  148  	if (pod)
b066303f Paul Burton 2015-05-24  149  		*pod = od;
b066303f Paul Burton 2015-05-24  150  
b066303f Paul Burton 2015-05-24  151  	return div_u64((u64)parent_rate * m, n * od);
b066303f Paul Burton 2015-05-24  152  }
b066303f Paul Burton 2015-05-24  153  

:::::: The code at line 137 was first introduced by commit
:::::: b066303fb3e72a902a1f94dc06636ce82c3a5577 clk: ingenic: add driver for Ingenic SoC CGU clocks

:::::: TO: Paul Burton <paul.burton@xxxxxxxxxx>
:::::: CC: Ralf Baechle <ralf@xxxxxxxxxxxxxx>

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