Re: [PATCH v2 02/12] iommu/vt-d: Manage scalalble mode PASID tables

[Lu Baolu]

Hi,

On 09/07/2018 07:43 AM, Jacob Pan wrote:
> On Thu, 6 Sep 2018 10:46:03 +0800
> Lu Baolu <baolu.lu@xxxxxxxxxxxxxxx> wrote:
>
> > > > @@ -224,7 +271,14 @@ struct pasid_entry
> > > > *intel_pasid_get_entry(struct device *dev, int pasid)
> > > >     */
> > > >    static inline void pasid_clear_entry(struct pasid_entry *pe)
> > > >    {
> > > > -	WRITE_ONCE(pe->val, 0);
> > > > +	WRITE_ONCE(pe->val[0], 0);
> > > > +	WRITE_ONCE(pe->val[1], 0);
> > > > +	WRITE_ONCE(pe->val[2], 0);
> > > > +	WRITE_ONCE(pe->val[3], 0);
> > > > +	WRITE_ONCE(pe->val[4], 0);
> > > > +	WRITE_ONCE(pe->val[5], 0);
> > > > +	WRITE_ONCE(pe->val[6], 0);
> > > > +	WRITE_ONCE(pe->val[7], 0);
> > >
> > > memset?
> >
> > The order is important here. Otherwise, the PRESENT bit of this pasid
> > entry might still set while other fields contains invalid values.
>
> WRITE_ONCE/READ_ONCE will switch to __builtin_memcpy() in if the size
> exceeds word size, ie. 64bit in this case. I don;t think compiler will
> reorder built-in function. Beside, we only need to clear present and
> FDP bit, right?

Clear present and FDP bit is enough for hardare. But from software point
of view, it's better to clear all bits with 0.

Best regards,
Lu Baolu