On 09/13/2018 05:57 PM, Guenter Roeck wrote:
On Thu, Sep 13, 2018 at 05:48:59PM +0200, CÃdric Le Goater wrote:
On 09/13/2018 03:33 PM, Guenter Roeck wrote:[ ... ]
That seems to suggest that none of the status bits auto-clears, and that /*
ÂÂ * The state machine needs some refinement. It is only used to track
ÂÂ * invalid STOP commands for the moment.
@@ -188,7 +215,7 @@ static void aspeed_i2c_bus_handle_cmd(AspeedI2CBus *bus, uint64_t value)
 {
ÂÂÂÂÂ bus->cmd &= ~0xFFFF;
ÂÂÂÂÂ bus->cmd |= value & 0xFFFF;
-ÂÂÂ bus->intr_status = 0;> +ÂÂÂ bus->intr_status &= I2CD_INTR_RX_DONE;
it deserves a comment to understand which scenario we are trying to handle.
Ok. FWIW, I wonder if intr_status should be touched here in the first place,
but I neither have the hardware nor a datasheet, so I don't know if any bits
are auto-cleared.
I just pushed a patch on my branch with some more explanation :
https://github.com/legoater/qemu/commits/aspeed-3.1
the above code clearing intr_status should be removed entirely.
Am I missing something ?
You are right. I just pushed another version of the previous patch with this
new hunk :
@@ -188,7 +200,6 @@ static void aspeed_i2c_bus_handle_cmd(As
{
bus->cmd &= ~0xFFFF;
bus->cmd |= value & 0xFFFF;
- bus->intr_status = 0;
if (bus->cmd & I2CD_M_START_CMD) {
uint8_t state = aspeed_i2c_get_state(bus) & I2CD_MACTIVE ?
The QEMU palmetto and witherspoon machines seem to behave fine. Can you give
it a try ?