Re: [PATCH v8 0/3] powerpc: Detection and scheduler optimization for POWER9 bigcore

[Dave Hansen]

On 09/20/2018 10:22 AM, Gautham R. Shenoy wrote:
>  	   -------------------------
> 	   |  	    L1 Cache       |
>        ----------------------------------
>        |L2|     |     |     |      |
>        |  |  0  |  2  |  4  |  6   |Small Core0
>        |C |     |     |     |      |
> Big    |a --------------------------
> Core   |c |     |     |     |      |
>        |h |  1  |  3  |  5  |  7   | Small Core1
>        |e |     |     |     |      |
>        -----------------------------
> 	  |  	    L1 Cache       |
> 	  --------------------------

The scheduler already knows about shared caches.  Could you elaborate on
how this is different from the situation today where we have multiple
cores sharing an L2/L3?

Adding the new sysfs stuff seems like overkill if that's all that you
are trying to do.