Re: [PATCH v2] Documentation/arm64: HugeTLB page implementation

[Catalin Marinas]

On Tue, Oct 09, 2018 at 12:50:49PM +0100, Will Deacon wrote:
> On Tue, Oct 09, 2018 at 11:02:01AM +0100, Punit Agrawal wrote:
> > Randy Dunlap <rdunlap@xxxxxxxxxxxxx> writes:
> > 
> > > On 10/8/18 3:03 AM, Punit Agrawal wrote:
> > >> Arm v8 architecture supports multiple page sizes - 4k, 16k and
> > >> 64k. Based on the active page size, the Linux port supports
> > >> corresponding hugepage sizes at PMD and PUD(4k only) levels.
> > >> 
> > >> In addition, the architecture also supports caching larger sized
> > >> ranges (composed of multiple entries) at the PTE and PMD level in the
> > >> TLBs using the contiguous bit. The Linux port makes use of this
> > >> architectural support to enable additional hugepage sizes.
> > >> 
> > >> Describe the two different types of hugepages supported by the arm64
> > >> kernel and the hugepage sizes enabled by each.
> > >> 
> > >> Signed-off-by: Punit Agrawal <punit.agrawal@xxxxxxx>
> > >> Cc: Catalin Marinas <catalin.marinas@xxxxxxx>
> > >> Cc: Will Deacon <will.deacon@xxxxxxx>
> > >> Cc: Jonathan Corbet <corbet@xxxxxxx>
> > >
> > > Acked-by: Randy Dunlap <rdunlap@xxxxxxxxxxxxx>
> > 
> > Thanks!
> > 
> > Catalin, Will - I assume you'll pick this up at some point? Or do arm64
> > documentation patches get routed by another tree?
> 
> Acked-by: Will Deacon <will.deacon@xxxxxxx>
> 
> Catalin can pick this up for 4.20.

Done.

-- 
Catalin